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2957 lines
66 KiB
2957 lines
66 KiB
// SPDX-License-Identifier: BSD-3-Clause |
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/* |
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* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. |
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* Copyright (c) 2019, Linaro Limited |
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*/ |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/qcom-aoss-qmp.h> |
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#include <dt-bindings/power/qcom-rpmpd.h> |
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#include <dt-bindings/soc/qcom,rpmh-rsc.h> |
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#include <dt-bindings/clock/qcom,rpmh.h> |
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#include <dt-bindings/clock/qcom,gcc-sm8150.h> |
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h> |
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#include <dt-bindings/interconnect/qcom,osm-l3.h> |
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#include <dt-bindings/thermal/thermal.h> |
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/ { |
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interrupt-parent = <&intc>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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chosen { }; |
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clocks { |
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xo_board: xo-board { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <38400000>; |
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clock-output-names = "xo_board"; |
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}; |
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sleep_clk: sleep-clk { |
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compatible = "fixed-clock"; |
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#clock-cells = <0>; |
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clock-frequency = <32764>; |
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clock-output-names = "sleep_clk"; |
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}; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <488>; |
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dynamic-power-coefficient = <232>; |
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next-level-cache = <&L2_0>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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power-domains = <&CPU_PD0>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_0: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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L3_0: l3-cache { |
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compatible = "cache"; |
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}; |
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}; |
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}; |
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CPU1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <488>; |
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dynamic-power-coefficient = <232>; |
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next-level-cache = <&L2_100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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power-domains = <&CPU_PD1>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_100: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <488>; |
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dynamic-power-coefficient = <232>; |
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next-level-cache = <&L2_200>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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power-domains = <&CPU_PD2>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_200: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <488>; |
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dynamic-power-coefficient = <232>; |
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next-level-cache = <&L2_300>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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power-domains = <&CPU_PD3>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_300: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x400>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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dynamic-power-coefficient = <369>; |
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next-level-cache = <&L2_400>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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power-domains = <&CPU_PD4>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_400: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x500>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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dynamic-power-coefficient = <369>; |
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next-level-cache = <&L2_500>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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power-domains = <&CPU_PD5>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_500: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU6: cpu@600 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x600>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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dynamic-power-coefficient = <369>; |
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next-level-cache = <&L2_600>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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power-domains = <&CPU_PD6>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_600: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU7: cpu@700 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo485"; |
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reg = <0x0 0x700>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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dynamic-power-coefficient = <421>; |
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next-level-cache = <&L2_700>; |
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qcom,freq-domain = <&cpufreq_hw 2>; |
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power-domains = <&CPU_PD7>; |
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power-domain-names = "psci"; |
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#cooling-cells = <2>; |
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L2_700: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&CPU0>; |
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}; |
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core1 { |
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cpu = <&CPU1>; |
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}; |
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core2 { |
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cpu = <&CPU2>; |
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}; |
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core3 { |
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cpu = <&CPU3>; |
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}; |
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core4 { |
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cpu = <&CPU4>; |
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}; |
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core5 { |
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cpu = <&CPU5>; |
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}; |
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core6 { |
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cpu = <&CPU6>; |
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}; |
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core7 { |
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cpu = <&CPU7>; |
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}; |
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}; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "little-rail-power-collapse"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <355>; |
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exit-latency-us = <909>; |
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min-residency-us = <3934>; |
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local-timer-stop; |
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}; |
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "big-rail-power-collapse"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <241>; |
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exit-latency-us = <1461>; |
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min-residency-us = <4488>; |
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local-timer-stop; |
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}; |
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}; |
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domain-idle-states { |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "domain-idle-state"; |
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idle-state-name = "cluster-power-collapse"; |
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arm,psci-suspend-param = <0x4100c244>; |
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entry-latency-us = <3263>; |
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exit-latency-us = <6562>; |
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min-residency-us = <9987>; |
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local-timer-stop; |
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}; |
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}; |
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}; |
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firmware { |
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scm: scm { |
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compatible = "qcom,scm-sm8150", "qcom,scm"; |
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#reset-cells = <1>; |
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}; |
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}; |
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tcsr_mutex: hwlock { |
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compatible = "qcom,tcsr-mutex"; |
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syscon = <&tcsr_mutex_regs 0 0x1000>; |
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#hwlock-cells = <1>; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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/* We expect the bootloader to fill in the size */ |
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reg = <0x0 0x80000000 0x0 0x0>; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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psci { |
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compatible = "arm,psci-1.0"; |
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method = "smc"; |
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CPU_PD0: cpu0 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
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}; |
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CPU_PD1: cpu1 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
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}; |
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CPU_PD2: cpu2 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
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}; |
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CPU_PD3: cpu3 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
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}; |
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CPU_PD4: cpu4 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&BIG_CPU_SLEEP_0>; |
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}; |
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CPU_PD5: cpu5 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&BIG_CPU_SLEEP_0>; |
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}; |
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CPU_PD6: cpu6 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&BIG_CPU_SLEEP_0>; |
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}; |
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CPU_PD7: cpu7 { |
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#power-domain-cells = <0>; |
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power-domains = <&CLUSTER_PD>; |
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domain-idle-states = <&BIG_CPU_SLEEP_0>; |
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}; |
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CLUSTER_PD: cpu-cluster0 { |
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#power-domain-cells = <0>; |
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domain-idle-states = <&CLUSTER_SLEEP_0>; |
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}; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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hyp_mem: memory@85700000 { |
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reg = <0x0 0x85700000 0x0 0x600000>; |
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no-map; |
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}; |
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xbl_mem: memory@85d00000 { |
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reg = <0x0 0x85d00000 0x0 0x140000>; |
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no-map; |
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}; |
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aop_mem: memory@85f00000 { |
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reg = <0x0 0x85f00000 0x0 0x20000>; |
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no-map; |
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}; |
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aop_cmd_db: memory@85f20000 { |
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compatible = "qcom,cmd-db"; |
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reg = <0x0 0x85f20000 0x0 0x20000>; |
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no-map; |
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}; |
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smem_mem: memory@86000000 { |
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reg = <0x0 0x86000000 0x0 0x200000>; |
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no-map; |
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}; |
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tz_mem: memory@86200000 { |
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reg = <0x0 0x86200000 0x0 0x3900000>; |
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no-map; |
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}; |
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rmtfs_mem: memory@89b00000 { |
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compatible = "qcom,rmtfs-mem"; |
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reg = <0x0 0x89b00000 0x0 0x200000>; |
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no-map; |
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qcom,client-id = <1>; |
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qcom,vmid = <15>; |
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}; |
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camera_mem: memory@8b700000 { |
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reg = <0x0 0x8b700000 0x0 0x500000>; |
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no-map; |
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}; |
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wlan_mem: memory@8bc00000 { |
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reg = <0x0 0x8bc00000 0x0 0x180000>; |
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no-map; |
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}; |
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npu_mem: memory@8bd80000 { |
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reg = <0x0 0x8bd80000 0x0 0x80000>; |
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no-map; |
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}; |
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adsp_mem: memory@8be00000 { |
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reg = <0x0 0x8be00000 0x0 0x1a00000>; |
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no-map; |
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}; |
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mpss_mem: memory@8d800000 { |
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reg = <0x0 0x8d800000 0x0 0x9600000>; |
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no-map; |
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}; |
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venus_mem: memory@96e00000 { |
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reg = <0x0 0x96e00000 0x0 0x500000>; |
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no-map; |
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}; |
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slpi_mem: memory@97300000 { |
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reg = <0x0 0x97300000 0x0 0x1400000>; |
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no-map; |
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}; |
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ipa_fw_mem: memory@98700000 { |
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reg = <0x0 0x98700000 0x0 0x10000>; |
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no-map; |
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}; |
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ipa_gsi_mem: memory@98710000 { |
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reg = <0x0 0x98710000 0x0 0x5000>; |
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no-map; |
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}; |
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gpu_mem: memory@98715000 { |
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reg = <0x0 0x98715000 0x0 0x2000>; |
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no-map; |
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}; |
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spss_mem: memory@98800000 { |
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reg = <0x0 0x98800000 0x0 0x100000>; |
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no-map; |
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}; |
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cdsp_mem: memory@98900000 { |
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reg = <0x0 0x98900000 0x0 0x1400000>; |
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no-map; |
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}; |
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qseecom_mem: memory@9e400000 { |
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reg = <0x0 0x9e400000 0x0 0x1400000>; |
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no-map; |
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}; |
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}; |
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smem { |
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compatible = "qcom,smem"; |
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memory-region = <&smem_mem>; |
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hwlocks = <&tcsr_mutex 3>; |
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}; |
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smp2p-cdsp { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <94>, <432>; |
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interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&apss_shared 6>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <5>; |
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cdsp_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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cdsp_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-lpass { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <443>, <429>; |
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interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&apss_shared 10>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <2>; |
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adsp_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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adsp_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-mpss { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <435>, <428>; |
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interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&apss_shared 14>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <1>; |
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modem_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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modem_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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smp2p-slpi { |
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compatible = "qcom,smp2p"; |
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qcom,smem = <481>, <430>; |
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interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; |
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mboxes = <&apss_shared 26>; |
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qcom,local-pid = <0>; |
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qcom,remote-pid = <3>; |
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slpi_smp2p_out: master-kernel { |
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qcom,entry-name = "master-kernel"; |
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#qcom,smem-state-cells = <1>; |
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}; |
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slpi_smp2p_in: slave-kernel { |
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qcom,entry-name = "slave-kernel"; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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}; |
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soc: soc@0 { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges = <0 0 0 0 0x10 0>; |
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dma-ranges = <0 0 0 0 0x10 0>; |
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compatible = "simple-bus"; |
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gcc: clock-controller@100000 { |
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compatible = "qcom,gcc-sm8150"; |
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reg = <0x0 0x00100000 0x0 0x1f0000>; |
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#clock-cells = <1>; |
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#reset-cells = <1>; |
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#power-domain-cells = <1>; |
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clock-names = "bi_tcxo", |
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"sleep_clk"; |
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clocks = <&rpmhcc RPMH_CXO_CLK>, |
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<&sleep_clk>; |
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}; |
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qupv3_id_1: geniqup@ac0000 { |
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compatible = "qcom,geni-se-qup"; |
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reg = <0x0 0x00ac0000 0x0 0x6000>; |
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clock-names = "m-ahb", "s-ahb"; |
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clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
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<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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status = "disabled"; |
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uart2: serial@a90000 { |
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compatible = "qcom,geni-debug-uart"; |
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reg = <0x0 0x00a90000 0x0 0x4000>; |
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clock-names = "se"; |
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clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
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interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
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status = "disabled"; |
|
}; |
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}; |
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|
|
config_noc: interconnect@1500000 { |
|
compatible = "qcom,sm8150-config-noc"; |
|
reg = <0 0x01500000 0 0x7400>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
system_noc: interconnect@1620000 { |
|
compatible = "qcom,sm8150-system-noc"; |
|
reg = <0 0x01620000 0 0x19400>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
mc_virt: interconnect@163a000 { |
|
compatible = "qcom,sm8150-mc-virt"; |
|
reg = <0 0x0163a000 0 0x1000>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre1_noc: interconnect@16e0000 { |
|
compatible = "qcom,sm8150-aggre1-noc"; |
|
reg = <0 0x016e0000 0 0xd080>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre2_noc: interconnect@1700000 { |
|
compatible = "qcom,sm8150-aggre2-noc"; |
|
reg = <0 0x01700000 0 0x20000>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
compute_noc: interconnect@1720000 { |
|
compatible = "qcom,sm8150-compute-noc"; |
|
reg = <0 0x01720000 0 0x7000>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
mmss_noc: interconnect@1740000 { |
|
compatible = "qcom,sm8150-mmss-noc"; |
|
reg = <0 0x01740000 0 0x1c100>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
system-cache-controller@9200000 { |
|
compatible = "qcom,sm8150-llcc"; |
|
reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; |
|
reg-names = "llcc_base", "llcc_broadcast_base"; |
|
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
ufs_mem_hc: ufshc@1d84000 { |
|
compatible = "qcom,sm8150-ufshc", "qcom,ufshc", |
|
"jedec,ufs-2.0"; |
|
reg = <0 0x01d84000 0 0x2500>; |
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
|
phys = <&ufs_mem_phy_lanes>; |
|
phy-names = "ufsphy"; |
|
lanes-per-direction = <2>; |
|
#reset-cells = <1>; |
|
resets = <&gcc GCC_UFS_PHY_BCR>; |
|
reset-names = "rst"; |
|
|
|
iommus = <&apps_smmu 0x300 0>; |
|
|
|
clock-names = |
|
"core_clk", |
|
"bus_aggr_clk", |
|
"iface_clk", |
|
"core_clk_unipro", |
|
"ref_clk", |
|
"tx_lane0_sync_clk", |
|
"rx_lane0_sync_clk", |
|
"rx_lane1_sync_clk"; |
|
clocks = |
|
<&gcc GCC_UFS_PHY_AXI_CLK>, |
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
|
<&gcc GCC_UFS_PHY_AHB_CLK>, |
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
|
freq-table-hz = |
|
<37500000 300000000>, |
|
<0 0>, |
|
<0 0>, |
|
<37500000 300000000>, |
|
<0 0>, |
|
<0 0>, |
|
<0 0>, |
|
<0 0>; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
ufs_mem_phy: phy@1d87000 { |
|
compatible = "qcom,sm8150-qmp-ufs-phy"; |
|
reg = <0 0x01d87000 0 0x1c0>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
clock-names = "ref", |
|
"ref_aux"; |
|
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, |
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
|
|
|
resets = <&ufs_mem_hc 0>; |
|
reset-names = "ufsphy"; |
|
status = "disabled"; |
|
|
|
ufs_mem_phy_lanes: lanes@1d87400 { |
|
reg = <0 0x01d87400 0 0x108>, |
|
<0 0x01d87600 0 0x1e0>, |
|
<0 0x01d87c00 0 0x1dc>, |
|
<0 0x01d87800 0 0x108>, |
|
<0 0x01d87a00 0 0x1e0>; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
|
|
ipa_virt: interconnect@1e00000 { |
|
compatible = "qcom,sm8150-ipa-virt"; |
|
reg = <0 0x01e00000 0 0x1000>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
tcsr_mutex_regs: syscon@1f40000 { |
|
compatible = "syscon"; |
|
reg = <0x0 0x01f40000 0x0 0x40000>; |
|
}; |
|
|
|
remoteproc_slpi: remoteproc@2400000 { |
|
compatible = "qcom,sm8150-slpi-pas"; |
|
reg = <0x0 0x02400000 0x0 0x4040>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>, |
|
<&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, |
|
<&rpmhpd 3>, |
|
<&rpmhpd 2>; |
|
power-domain-names = "load_state", "lcx", "lmx"; |
|
|
|
memory-region = <&slpi_mem>; |
|
|
|
qcom,smem-states = <&slpi_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
status = "disabled"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; |
|
label = "dsps"; |
|
qcom,remote-pid = <3>; |
|
mboxes = <&apss_shared 24>; |
|
}; |
|
}; |
|
|
|
gpu: gpu@2c00000 { |
|
/* |
|
* note: the amd,imageon compatible makes it possible |
|
* to use the drm/msm driver without the display node, |
|
* make sure to remove it when display node is added |
|
*/ |
|
compatible = "qcom,adreno-640.1", |
|
"qcom,adreno", |
|
"amd,imageon"; |
|
#stream-id-cells = <16>; |
|
|
|
reg = <0 0x02c00000 0 0x40000>; |
|
reg-names = "kgsl_3d0_reg_memory"; |
|
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
iommus = <&adreno_smmu 0 0x401>; |
|
|
|
operating-points-v2 = <&gpu_opp_table>; |
|
|
|
qcom,gmu = <&gmu>; |
|
|
|
zap-shader { |
|
memory-region = <&gpu_mem>; |
|
}; |
|
|
|
/* note: downstream checks gpu binning for 675 Mhz */ |
|
gpu_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-675000000 { |
|
opp-hz = /bits/ 64 <675000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
|
}; |
|
|
|
opp-585000000 { |
|
opp-hz = /bits/ 64 <585000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
|
}; |
|
|
|
opp-499200000 { |
|
opp-hz = /bits/ 64 <499200000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
|
}; |
|
|
|
opp-427000000 { |
|
opp-hz = /bits/ 64 <427000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
|
}; |
|
|
|
opp-345000000 { |
|
opp-hz = /bits/ 64 <345000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
}; |
|
|
|
opp-257000000 { |
|
opp-hz = /bits/ 64 <257000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
|
}; |
|
}; |
|
}; |
|
|
|
gmu: gmu@2c6a000 { |
|
compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu"; |
|
|
|
reg = <0 0x02c6a000 0 0x30000>, |
|
<0 0x0b290000 0 0x10000>, |
|
<0 0x0b490000 0 0x10000>; |
|
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; |
|
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hfi", "gmu"; |
|
|
|
clocks = <&gpucc GPU_CC_AHB_CLK>, |
|
<&gpucc GPU_CC_CX_GMU_CLK>, |
|
<&gpucc GPU_CC_CXO_CLK>, |
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>, |
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>; |
|
clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; |
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>, |
|
<&gpucc GPU_GX_GDSC>; |
|
power-domain-names = "cx", "gx"; |
|
|
|
iommus = <&adreno_smmu 5 0x400>; |
|
|
|
operating-points-v2 = <&gmu_opp_table>; |
|
|
|
gmu_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-200000000 { |
|
opp-hz = /bits/ 64 <200000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
|
}; |
|
}; |
|
}; |
|
|
|
gpucc: clock-controller@2c90000 { |
|
compatible = "qcom,sm8150-gpucc"; |
|
reg = <0 0x02c90000 0 0x9000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>, |
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
|
clock-names = "bi_tcxo", |
|
"gcc_gpu_gpll0_clk_src", |
|
"gcc_gpu_gpll0_div_clk_src"; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
adreno_smmu: iommu@2ca0000 { |
|
compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; |
|
reg = <0 0x02ca0000 0 0x10000>; |
|
#iommu-cells = <2>; |
|
#global-interrupts = <1>; |
|
interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&gpucc GPU_CC_AHB_CLK>, |
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
|
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; |
|
clock-names = "ahb", "bus", "iface"; |
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>; |
|
}; |
|
|
|
tlmm: pinctrl@3100000 { |
|
compatible = "qcom,sm8150-pinctrl"; |
|
reg = <0x0 0x03100000 0x0 0x300000>, |
|
<0x0 0x03500000 0x0 0x300000>, |
|
<0x0 0x03900000 0x0 0x300000>, |
|
<0x0 0x03D00000 0x0 0x300000>; |
|
reg-names = "west", "east", "north", "south"; |
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-ranges = <&tlmm 0 0 176>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
|
|
remoteproc_mpss: remoteproc@4080000 { |
|
compatible = "qcom,sm8150-mpss-pas"; |
|
reg = <0x0 0x04080000 0x0 0x4040>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", "handover", |
|
"stop-ack", "shutdown-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, |
|
<&rpmhpd 7>, |
|
<&rpmhpd 0>; |
|
power-domain-names = "load_state", "cx", "mss"; |
|
|
|
memory-region = <&mpss_mem>; |
|
|
|
qcom,smem-states = <&modem_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
|
label = "modem"; |
|
qcom,remote-pid = <1>; |
|
mboxes = <&apss_shared 12>; |
|
}; |
|
}; |
|
|
|
stm@6002000 { |
|
compatible = "arm,coresight-stm", "arm,primecell"; |
|
reg = <0 0x06002000 0 0x1000>, |
|
<0 0x16280000 0 0x180000>; |
|
reg-names = "stm-base", "stm-stimulus-base"; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
stm_out: endpoint { |
|
remote-endpoint = <&funnel0_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6041000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06041000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel0_out: endpoint { |
|
remote-endpoint = <&merge_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@7 { |
|
reg = <7>; |
|
funnel0_in7: endpoint { |
|
remote-endpoint = <&stm_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6042000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06042000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel1_out: endpoint { |
|
remote-endpoint = <&merge_funnel_in1>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@4 { |
|
reg = <4>; |
|
funnel1_in4: endpoint { |
|
remote-endpoint = <&swao_replicator_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6043000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06043000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel2_out: endpoint { |
|
remote-endpoint = <&merge_funnel_in2>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@2 { |
|
reg = <2>; |
|
funnel2_in2: endpoint { |
|
remote-endpoint = <&apss_merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6045000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06045000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
merge_funnel_out: endpoint { |
|
remote-endpoint = <&etf_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
merge_funnel_in0: endpoint { |
|
remote-endpoint = <&funnel0_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
merge_funnel_in1: endpoint { |
|
remote-endpoint = <&funnel1_out>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <2>; |
|
merge_funnel_in2: endpoint { |
|
remote-endpoint = <&funnel2_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@6046000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x06046000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
replicator_out0: endpoint { |
|
remote-endpoint = <&etr_in>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
replicator_out1: endpoint { |
|
remote-endpoint = <&replicator1_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
replicator_in0: endpoint { |
|
remote-endpoint = <&etf_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etf@6047000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06047000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etf_out: endpoint { |
|
remote-endpoint = <&replicator_in0>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
etf_in: endpoint { |
|
remote-endpoint = <&merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etr@6048000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06048000 0 0x1000>; |
|
iommus = <&apps_smmu 0x05e0 0x0>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,scatter-gather; |
|
|
|
in-ports { |
|
port { |
|
etr_in: endpoint { |
|
remote-endpoint = <&replicator_out0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@604a000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x0604a000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@1 { |
|
reg = <1>; |
|
replicator1_out: endpoint { |
|
remote-endpoint = <&swao_funnel_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@1 { |
|
reg = <1>; |
|
replicator1_in: endpoint { |
|
remote-endpoint = <&replicator_out1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6b08000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06b08000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
swao_funnel_out: endpoint { |
|
remote-endpoint = <&swao_etf_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@6 { |
|
reg = <6>; |
|
swao_funnel_in: endpoint { |
|
remote-endpoint = <&replicator1_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etf@6b09000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06b09000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
swao_etf_out: endpoint { |
|
remote-endpoint = <&swao_replicator_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
swao_etf_in: endpoint { |
|
remote-endpoint = <&swao_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@6b0a000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x06b0a000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
qcom,replicator-loses-context; |
|
|
|
out-ports { |
|
port { |
|
swao_replicator_out: endpoint { |
|
remote-endpoint = <&funnel1_in4>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
swao_replicator_in: endpoint { |
|
remote-endpoint = <&swao_etf_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7040000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07040000 0 0x1000>; |
|
|
|
cpu = <&CPU0>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm0_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7140000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07140000 0 0x1000>; |
|
|
|
cpu = <&CPU1>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm1_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7240000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07240000 0 0x1000>; |
|
|
|
cpu = <&CPU2>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm2_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in2>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7340000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07340000 0 0x1000>; |
|
|
|
cpu = <&CPU3>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm3_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in3>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7440000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07440000 0 0x1000>; |
|
|
|
cpu = <&CPU4>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm4_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in4>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7540000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07540000 0 0x1000>; |
|
|
|
cpu = <&CPU5>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm5_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in5>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7640000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07640000 0 0x1000>; |
|
|
|
cpu = <&CPU6>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm6_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in6>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7740000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07740000 0 0x1000>; |
|
|
|
cpu = <&CPU7>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
qcom,skip-power-up; |
|
|
|
out-ports { |
|
port { |
|
etm7_out: endpoint { |
|
remote-endpoint = <&apss_funnel_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7800000 { /* APSS Funnel */ |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07800000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_funnel_out: endpoint { |
|
remote-endpoint = <&apss_merge_funnel_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
apss_funnel_in0: endpoint { |
|
remote-endpoint = <&etm0_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
apss_funnel_in1: endpoint { |
|
remote-endpoint = <&etm1_out>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <2>; |
|
apss_funnel_in2: endpoint { |
|
remote-endpoint = <&etm2_out>; |
|
}; |
|
}; |
|
|
|
port@3 { |
|
reg = <3>; |
|
apss_funnel_in3: endpoint { |
|
remote-endpoint = <&etm3_out>; |
|
}; |
|
}; |
|
|
|
port@4 { |
|
reg = <4>; |
|
apss_funnel_in4: endpoint { |
|
remote-endpoint = <&etm4_out>; |
|
}; |
|
}; |
|
|
|
port@5 { |
|
reg = <5>; |
|
apss_funnel_in5: endpoint { |
|
remote-endpoint = <&etm5_out>; |
|
}; |
|
}; |
|
|
|
port@6 { |
|
reg = <6>; |
|
apss_funnel_in6: endpoint { |
|
remote-endpoint = <&etm6_out>; |
|
}; |
|
}; |
|
|
|
port@7 { |
|
reg = <7>; |
|
apss_funnel_in7: endpoint { |
|
remote-endpoint = <&etm7_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7810000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07810000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_merge_funnel_out: endpoint { |
|
remote-endpoint = <&funnel2_in2>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
apss_merge_funnel_in: endpoint { |
|
remote-endpoint = <&apss_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
remoteproc_cdsp: remoteproc@8300000 { |
|
compatible = "qcom,sm8150-cdsp-pas"; |
|
reg = <0x0 0x08300000 0x0 0x4040>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, |
|
<&rpmhpd 7>; |
|
power-domain-names = "load_state", "cx"; |
|
|
|
memory-region = <&cdsp_mem>; |
|
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
status = "disabled"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
|
label = "cdsp"; |
|
qcom,remote-pid = <5>; |
|
mboxes = <&apss_shared 4>; |
|
}; |
|
}; |
|
|
|
usb_1_hsphy: phy@88e2000 { |
|
compatible = "qcom,sm8150-usb-hs-phy", |
|
"qcom,usb-snps-hs-7nm-phy"; |
|
reg = <0 0x088e2000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
|
}; |
|
|
|
usb_2_hsphy: phy@88e3000 { |
|
compatible = "qcom,sm8150-usb-hs-phy", |
|
"qcom,usb-snps-hs-7nm-phy"; |
|
reg = <0 0x088e3000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
|
}; |
|
|
|
usb_1_qmpphy: phy@88e9000 { |
|
compatible = "qcom,sm8150-qmp-usb3-phy"; |
|
reg = <0 0x088e9000 0 0x18c>, |
|
<0 0x088e8000 0 0x10>; |
|
reg-names = "reg-base", "dp_com"; |
|
status = "disabled"; |
|
#clock-cells = <1>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_USB3_PRIM_CLKREF_CLK>, |
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
|
clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
|
|
|
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
|
<&gcc GCC_USB3_PHY_PRIM_BCR>; |
|
reset-names = "phy", "common"; |
|
|
|
usb_1_ssphy: lanes@88e9200 { |
|
reg = <0 0x088e9200 0 0x200>, |
|
<0 0x088e9400 0 0x200>, |
|
<0 0x088e9c00 0 0x218>, |
|
<0 0x088e9600 0 0x200>, |
|
<0 0x088e9800 0 0x200>, |
|
<0 0x088e9a00 0 0x100>; |
|
#phy-cells = <0>; |
|
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_phy_pipe_clk_src"; |
|
}; |
|
}; |
|
|
|
dc_noc: interconnect@9160000 { |
|
compatible = "qcom,sm8150-dc-noc"; |
|
reg = <0 0x09160000 0 0x3200>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
gem_noc: interconnect@9680000 { |
|
compatible = "qcom,sm8150-gem-noc"; |
|
reg = <0 0x09680000 0 0x3e200>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
usb_2_qmpphy: phy@88eb000 { |
|
compatible = "qcom,sm8150-qmp-usb3-uni-phy"; |
|
reg = <0 0x088eb000 0 0x200>; |
|
status = "disabled"; |
|
#clock-cells = <1>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>, |
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
|
clock-names = "aux", "ref_clk_src", "ref", "com_aux"; |
|
|
|
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
|
<&gcc GCC_USB3_PHY_SEC_BCR>; |
|
reset-names = "phy", "common"; |
|
|
|
usb_2_ssphy: lane@88eb200 { |
|
reg = <0 0x088eb200 0 0x200>, |
|
<0 0x088eb400 0 0x200>, |
|
<0 0x088eb800 0 0x800>, |
|
<0 0x088eb600 0 0x200>; |
|
#phy-cells = <0>; |
|
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
|
}; |
|
}; |
|
|
|
usb_1: usb@a6f8800 { |
|
compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; |
|
reg = <0 0x0a6f8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>, |
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>; |
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
|
"sleep", "xo"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <200000000>; |
|
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hs_phy_irq", "ss_phy_irq", |
|
"dm_hs_phy_irq", "dp_hs_phy_irq"; |
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>; |
|
|
|
usb_1_dwc3: dwc3@a600000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x0a600000 0 0xcd00>; |
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x140 0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_1_hsphy>, <&usb_1_ssphy>; |
|
phy-names = "usb2-phy", "usb3-phy"; |
|
}; |
|
}; |
|
|
|
usb_2: usb@a8f8800 { |
|
compatible = "qcom,sm8150-dwc3", "qcom,dwc3"; |
|
reg = <0 0x0a8f8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>, |
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>; |
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
|
"sleep", "xo"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <200000000>; |
|
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hs_phy_irq", "ss_phy_irq", |
|
"dm_hs_phy_irq", "dp_hs_phy_irq"; |
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>; |
|
|
|
usb_2_dwc3: dwc3@a800000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x0a800000 0 0xcd00>; |
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x160 0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_2_hsphy>, <&usb_2_ssphy>; |
|
phy-names = "usb2-phy", "usb3-phy"; |
|
}; |
|
}; |
|
|
|
camnoc_virt: interconnect@ac00000 { |
|
compatible = "qcom,sm8150-camnoc-virt"; |
|
reg = <0 0x0ac00000 0 0x1000>; |
|
#interconnect-cells = <1>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aoss_qmp: power-controller@c300000 { |
|
compatible = "qcom,sm8150-aoss-qmp"; |
|
reg = <0x0 0x0c300000 0x0 0x100000>; |
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; |
|
mboxes = <&apss_shared 0>; |
|
|
|
#clock-cells = <0>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
tsens0: thermal-sensor@c263000 { |
|
compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; |
|
reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
|
<0 0x0c222000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <16>; |
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow", "critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
tsens1: thermal-sensor@c265000 { |
|
compatible = "qcom,sm8150-tsens", "qcom,tsens-v2"; |
|
reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
|
<0 0x0c223000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <8>; |
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow", "critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
spmi_bus: spmi@c440000 { |
|
compatible = "qcom,spmi-pmic-arb"; |
|
reg = <0x0 0x0c440000 0x0 0x0001100>, |
|
<0x0 0x0c600000 0x0 0x2000000>, |
|
<0x0 0x0e600000 0x0 0x0100000>, |
|
<0x0 0x0e700000 0x0 0x00a0000>, |
|
<0x0 0x0c40a000 0x0 0x0026000>; |
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
|
interrupt-names = "periph_irq"; |
|
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,ee = <0>; |
|
qcom,channel = <0>; |
|
#address-cells = <2>; |
|
#size-cells = <0>; |
|
interrupt-controller; |
|
#interrupt-cells = <4>; |
|
cell-index = <0>; |
|
}; |
|
|
|
apps_smmu: iommu@15000000 { |
|
compatible = "qcom,sm8150-smmu-500", "arm,mmu-500"; |
|
reg = <0 0x15000000 0 0x100000>; |
|
#iommu-cells = <2>; |
|
#global-interrupts = <1>; |
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
remoteproc_adsp: remoteproc@17300000 { |
|
compatible = "qcom,sm8150-adsp-pas"; |
|
reg = <0x0 0x17300000 0x0 0x4040>; |
|
|
|
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, |
|
<&rpmhpd 7>; |
|
power-domain-names = "load_state", "cx"; |
|
|
|
memory-region = <&adsp_mem>; |
|
|
|
qcom,smem-states = <&adsp_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
status = "disabled"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
|
label = "lpass"; |
|
qcom,remote-pid = <2>; |
|
mboxes = <&apss_shared 8>; |
|
}; |
|
}; |
|
|
|
intc: interrupt-controller@17a00000 { |
|
compatible = "arm,gic-v3"; |
|
interrupt-controller; |
|
#interrupt-cells = <3>; |
|
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ |
|
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ |
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
apss_shared: mailbox@17c00000 { |
|
compatible = "qcom,sm8150-apss-shared"; |
|
reg = <0x0 0x17c00000 0x0 0x1000>; |
|
#mbox-cells = <1>; |
|
}; |
|
|
|
watchdog@17c10000 { |
|
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt"; |
|
reg = <0 0x17c10000 0 0x1000>; |
|
clocks = <&sleep_clk>; |
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
timer@17c20000 { |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
compatible = "arm,armv7-timer-mem"; |
|
reg = <0x0 0x17c20000 0x0 0x1000>; |
|
clock-frequency = <19200000>; |
|
|
|
frame@17c21000{ |
|
frame-number = <0>; |
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c21000 0x0 0x1000>, |
|
<0x0 0x17c22000 0x0 0x1000>; |
|
}; |
|
|
|
frame@17c23000 { |
|
frame-number = <1>; |
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c23000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c25000 { |
|
frame-number = <2>; |
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c25000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c27000 { |
|
frame-number = <3>; |
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c26000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c29000 { |
|
frame-number = <4>; |
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c29000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c2b000 { |
|
frame-number = <5>; |
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c2b000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17c2d000 { |
|
frame-number = <6>; |
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0x0 0x17c2d000 0x0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
apps_rsc: rsc@18200000 { |
|
label = "apps_rsc"; |
|
compatible = "qcom,rpmh-rsc"; |
|
reg = <0x0 0x18200000 0x0 0x10000>, |
|
<0x0 0x18210000 0x0 0x10000>, |
|
<0x0 0x18220000 0x0 0x10000>; |
|
reg-names = "drv-0", "drv-1", "drv-2"; |
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,tcs-offset = <0xd00>; |
|
qcom,drv-id = <2>; |
|
qcom,tcs-config = <ACTIVE_TCS 2>, |
|
<SLEEP_TCS 1>, |
|
<WAKE_TCS 1>, |
|
<CONTROL_TCS 0>; |
|
|
|
rpmhcc: clock-controller { |
|
compatible = "qcom,sm8150-rpmh-clk"; |
|
#clock-cells = <1>; |
|
clock-names = "xo"; |
|
clocks = <&xo_board>; |
|
}; |
|
|
|
rpmhpd: power-controller { |
|
compatible = "qcom,sm8150-rpmhpd"; |
|
#power-domain-cells = <1>; |
|
operating-points-v2 = <&rpmhpd_opp_table>; |
|
|
|
rpmhpd_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
rpmhpd_opp_ret: opp1 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
|
}; |
|
|
|
rpmhpd_opp_min_svs: opp2 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_low_svs: opp3 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs: opp4 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs_l1: opp5 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
|
}; |
|
|
|
rpmhpd_opp_svs_l2: opp6 { |
|
opp-level = <224>; |
|
}; |
|
|
|
rpmhpd_opp_nom: opp7 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
|
}; |
|
|
|
rpmhpd_opp_nom_l1: opp8 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
|
}; |
|
|
|
rpmhpd_opp_nom_l2: opp9 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
|
}; |
|
|
|
rpmhpd_opp_turbo: opp10 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
|
}; |
|
|
|
rpmhpd_opp_turbo_l1: opp11 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
|
}; |
|
}; |
|
}; |
|
|
|
apps_bcm_voter: bcm_voter { |
|
compatible = "qcom,bcm-voter"; |
|
}; |
|
}; |
|
|
|
osm_l3: interconnect@18321000 { |
|
compatible = "qcom,sm8150-osm-l3"; |
|
reg = <0 0x18321000 0 0x1400>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
|
clock-names = "xo", "alternate"; |
|
|
|
#interconnect-cells = <1>; |
|
}; |
|
|
|
cpufreq_hw: cpufreq@18323000 { |
|
compatible = "qcom,cpufreq-hw"; |
|
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>, |
|
<0 0x18327800 0 0x1400>; |
|
reg-names = "freq-domain0", "freq-domain1", |
|
"freq-domain2"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
|
clock-names = "xo", "alternate"; |
|
|
|
#freq-domain-cells = <1>; |
|
}; |
|
|
|
wifi: wifi@18800000 { |
|
compatible = "qcom,wcn3990-wifi"; |
|
reg = <0 0x18800000 0 0x800000>; |
|
reg-names = "membase"; |
|
memory-region = <&wlan_mem>; |
|
clock-names = "cxo_ref_clk_pin", "qdss"; |
|
clocks = <&rpmhcc RPMH_RF_CLK2>, <&aoss_qmp>; |
|
interrupts = <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x0640 0x1>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
|
}; |
|
|
|
thermal-zones { |
|
cpu0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 1>; |
|
|
|
trips { |
|
cpu0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu0_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu0_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 2>; |
|
|
|
trips { |
|
cpu1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu1_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu1_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu2-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 3>; |
|
|
|
trips { |
|
cpu2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu2_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu2_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu3-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 4>; |
|
|
|
trips { |
|
cpu3_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu3_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu3_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu4-top-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 7>; |
|
|
|
trips { |
|
cpu4_top_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_top_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_top_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu4_top_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu4_top_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu5-top-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 8>; |
|
|
|
trips { |
|
cpu5_top_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_top_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_top_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu5_top_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu5_top_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu6-top-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 9>; |
|
|
|
trips { |
|
cpu6_top_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_top_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_top_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu6_top_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu6_top_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu7-top-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 10>; |
|
|
|
trips { |
|
cpu7_top_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_top_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_top_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu7_top_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu7_top_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu4-bottom-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 11>; |
|
|
|
trips { |
|
cpu4_bottom_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_bottom_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_bottom_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu4_bottom_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu4_bottom_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu5-bottom-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 12>; |
|
|
|
trips { |
|
cpu5_bottom_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_bottom_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_bottom_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu5_bottom_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu5_bottom_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu6-bottom-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 13>; |
|
|
|
trips { |
|
cpu6_bottom_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_bottom_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_bottom_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu6_bottom_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu6_bottom_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu7-bottom-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 14>; |
|
|
|
trips { |
|
cpu7_bottom_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_bottom_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_bottom_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu7_bottom_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu7_bottom_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 0>; |
|
|
|
trips { |
|
aoss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
cluster0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 5>; |
|
|
|
trips { |
|
cluster0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cluster0_crit: cluster0_crit { |
|
temperature = <110000>; |
|
hysteresis = <2000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
cluster1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 6>; |
|
|
|
trips { |
|
cluster1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cluster1_crit: cluster1_crit { |
|
temperature = <110000>; |
|
hysteresis = <2000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu-thermal-top { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 15>; |
|
|
|
trips { |
|
gpu1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 0>; |
|
|
|
trips { |
|
aoss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
wlan-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 1>; |
|
|
|
trips { |
|
wlan_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
video-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 2>; |
|
|
|
trips { |
|
video_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
mem-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 3>; |
|
|
|
trips { |
|
mem_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
q6-hvx-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 4>; |
|
|
|
trips { |
|
q6_hvx_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
camera-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 5>; |
|
|
|
trips { |
|
camera_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
compute-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 6>; |
|
|
|
trips { |
|
compute_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
modem-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 7>; |
|
|
|
trips { |
|
modem_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
npu-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 8>; |
|
|
|
trips { |
|
npu_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
modem-vec-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 9>; |
|
|
|
trips { |
|
modem_vec_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
modem-scl-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 10>; |
|
|
|
trips { |
|
modem_scl_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu-thermal-bottom { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 11>; |
|
|
|
trips { |
|
gpu2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
}; |
|
};
|
|
|