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5356 lines
131 KiB
5356 lines
131 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* SDM845 SoC device tree source |
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* |
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* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
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*/ |
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|
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#include <dt-bindings/clock/qcom,camcc-sdm845.h> |
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h> |
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
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#include <dt-bindings/clock/qcom,lpass-sdm845.h> |
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#include <dt-bindings/clock/qcom,rpmh.h> |
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#include <dt-bindings/clock/qcom,videocc-sdm845.h> |
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#include <dt-bindings/interconnect/qcom,osm-l3.h> |
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#include <dt-bindings/interconnect/qcom,sdm845.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/phy/phy-qcom-qusb2.h> |
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#include <dt-bindings/power/qcom-rpmpd.h> |
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#include <dt-bindings/reset/qcom,sdm845-aoss.h> |
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#include <dt-bindings/reset/qcom,sdm845-pdc.h> |
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#include <dt-bindings/soc/qcom,apr.h> |
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#include <dt-bindings/soc/qcom,rpmh-rsc.h> |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h> |
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#include <dt-bindings/thermal/thermal.h> |
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/ { |
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interrupt-parent = <&intc>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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aliases { |
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i2c0 = &i2c0; |
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i2c1 = &i2c1; |
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i2c2 = &i2c2; |
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i2c3 = &i2c3; |
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i2c4 = &i2c4; |
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i2c5 = &i2c5; |
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i2c6 = &i2c6; |
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i2c7 = &i2c7; |
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i2c8 = &i2c8; |
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i2c9 = &i2c9; |
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i2c10 = &i2c10; |
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i2c11 = &i2c11; |
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i2c12 = &i2c12; |
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i2c13 = &i2c13; |
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i2c14 = &i2c14; |
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i2c15 = &i2c15; |
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spi0 = &spi0; |
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spi1 = &spi1; |
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spi2 = &spi2; |
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spi3 = &spi3; |
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spi4 = &spi4; |
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spi5 = &spi5; |
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spi6 = &spi6; |
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spi7 = &spi7; |
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spi8 = &spi8; |
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spi9 = &spi9; |
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spi10 = &spi10; |
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spi11 = &spi11; |
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spi12 = &spi12; |
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spi13 = &spi13; |
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spi14 = &spi14; |
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spi15 = &spi15; |
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}; |
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chosen { }; |
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memory@80000000 { |
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device_type = "memory"; |
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/* We expect the bootloader to fill in the size */ |
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reg = <0 0x80000000 0 0>; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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hyp_mem: memory@85700000 { |
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reg = <0 0x85700000 0 0x600000>; |
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no-map; |
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}; |
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xbl_mem: memory@85e00000 { |
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reg = <0 0x85e00000 0 0x100000>; |
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no-map; |
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}; |
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aop_mem: memory@85fc0000 { |
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reg = <0 0x85fc0000 0 0x20000>; |
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no-map; |
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}; |
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aop_cmd_db_mem: memory@85fe0000 { |
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compatible = "qcom,cmd-db"; |
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reg = <0x0 0x85fe0000 0 0x20000>; |
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no-map; |
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}; |
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smem_mem: memory@86000000 { |
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reg = <0x0 0x86000000 0 0x200000>; |
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no-map; |
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}; |
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tz_mem: memory@86200000 { |
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reg = <0 0x86200000 0 0x2d00000>; |
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no-map; |
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}; |
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rmtfs_mem: memory@88f00000 { |
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compatible = "qcom,rmtfs-mem"; |
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reg = <0 0x88f00000 0 0x200000>; |
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no-map; |
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qcom,client-id = <1>; |
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qcom,vmid = <15>; |
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}; |
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qseecom_mem: memory@8ab00000 { |
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reg = <0 0x8ab00000 0 0x1400000>; |
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no-map; |
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}; |
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camera_mem: memory@8bf00000 { |
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reg = <0 0x8bf00000 0 0x500000>; |
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no-map; |
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}; |
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ipa_fw_mem: memory@8c400000 { |
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reg = <0 0x8c400000 0 0x10000>; |
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no-map; |
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}; |
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ipa_gsi_mem: memory@8c410000 { |
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reg = <0 0x8c410000 0 0x5000>; |
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no-map; |
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}; |
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gpu_mem: memory@8c415000 { |
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reg = <0 0x8c415000 0 0x2000>; |
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no-map; |
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}; |
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adsp_mem: memory@8c500000 { |
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reg = <0 0x8c500000 0 0x1a00000>; |
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no-map; |
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}; |
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wlan_msa_mem: memory@8df00000 { |
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reg = <0 0x8df00000 0 0x100000>; |
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no-map; |
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}; |
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mpss_region: memory@8e000000 { |
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reg = <0 0x8e000000 0 0x7800000>; |
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no-map; |
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}; |
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venus_mem: memory@95800000 { |
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reg = <0 0x95800000 0 0x500000>; |
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no-map; |
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}; |
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cdsp_mem: memory@95d00000 { |
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reg = <0 0x95d00000 0 0x800000>; |
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no-map; |
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}; |
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mba_region: memory@96500000 { |
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reg = <0 0x96500000 0 0x200000>; |
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no-map; |
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}; |
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slpi_mem: memory@96700000 { |
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reg = <0 0x96700000 0 0x1400000>; |
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no-map; |
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}; |
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spss_mem: memory@97b00000 { |
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reg = <0 0x97b00000 0 0x100000>; |
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no-map; |
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}; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <607>; |
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dynamic-power-coefficient = <100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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operating-points-v2 = <&cpu0_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_0>; |
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L2_0: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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L3_0: l3-cache { |
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compatible = "cache"; |
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}; |
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}; |
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}; |
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CPU1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <607>; |
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dynamic-power-coefficient = <100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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operating-points-v2 = <&cpu0_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_100>; |
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L2_100: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <607>; |
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dynamic-power-coefficient = <100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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operating-points-v2 = <&cpu0_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_200>; |
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L2_200: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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cpu-idle-states = <&LITTLE_CPU_SLEEP_0 |
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&LITTLE_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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capacity-dmips-mhz = <607>; |
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dynamic-power-coefficient = <100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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operating-points-v2 = <&cpu0_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_300>; |
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L2_300: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x400>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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dynamic-power-coefficient = <396>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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operating-points-v2 = <&cpu4_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_400>; |
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L2_400: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x500>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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dynamic-power-coefficient = <396>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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operating-points-v2 = <&cpu4_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_500>; |
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L2_500: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU6: cpu@600 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x600>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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dynamic-power-coefficient = <396>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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operating-points-v2 = <&cpu4_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_600>; |
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L2_600: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU7: cpu@700 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x700>; |
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enable-method = "psci"; |
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capacity-dmips-mhz = <1024>; |
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cpu-idle-states = <&BIG_CPU_SLEEP_0 |
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&BIG_CPU_SLEEP_1 |
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&CLUSTER_SLEEP_0>; |
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dynamic-power-coefficient = <396>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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operating-points-v2 = <&cpu4_opp_table>; |
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interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, |
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<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; |
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#cooling-cells = <2>; |
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next-level-cache = <&L2_700>; |
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L2_700: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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cpu-map { |
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cluster0 { |
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core0 { |
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cpu = <&CPU0>; |
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}; |
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core1 { |
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cpu = <&CPU1>; |
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}; |
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core2 { |
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cpu = <&CPU2>; |
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}; |
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core3 { |
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cpu = <&CPU3>; |
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}; |
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core4 { |
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cpu = <&CPU4>; |
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}; |
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core5 { |
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cpu = <&CPU5>; |
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}; |
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core6 { |
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cpu = <&CPU6>; |
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}; |
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core7 { |
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cpu = <&CPU7>; |
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}; |
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}; |
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}; |
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idle-states { |
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entry-method = "psci"; |
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LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "little-power-down"; |
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arm,psci-suspend-param = <0x40000003>; |
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entry-latency-us = <350>; |
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exit-latency-us = <461>; |
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min-residency-us = <1890>; |
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local-timer-stop; |
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}; |
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LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "little-rail-power-down"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <360>; |
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exit-latency-us = <531>; |
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min-residency-us = <3934>; |
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local-timer-stop; |
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}; |
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BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "big-power-down"; |
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arm,psci-suspend-param = <0x40000003>; |
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entry-latency-us = <264>; |
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exit-latency-us = <621>; |
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min-residency-us = <952>; |
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local-timer-stop; |
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}; |
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BIG_CPU_SLEEP_1: cpu-sleep-1-1 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "big-rail-power-down"; |
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arm,psci-suspend-param = <0x40000004>; |
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entry-latency-us = <702>; |
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exit-latency-us = <1061>; |
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min-residency-us = <4488>; |
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local-timer-stop; |
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}; |
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CLUSTER_SLEEP_0: cluster-sleep-0 { |
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compatible = "arm,idle-state"; |
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idle-state-name = "cluster-power-down"; |
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arm,psci-suspend-param = <0x400000F4>; |
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entry-latency-us = <3263>; |
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exit-latency-us = <6562>; |
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min-residency-us = <9987>; |
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local-timer-stop; |
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}; |
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}; |
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}; |
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cpu0_opp_table: cpu0_opp_table { |
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compatible = "operating-points-v2"; |
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opp-shared; |
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cpu0_opp1: opp-300000000 { |
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opp-hz = /bits/ 64 <300000000>; |
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opp-peak-kBps = <800000 4800000>; |
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}; |
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cpu0_opp2: opp-403200000 { |
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opp-hz = /bits/ 64 <403200000>; |
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opp-peak-kBps = <800000 4800000>; |
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}; |
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cpu0_opp3: opp-480000000 { |
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opp-hz = /bits/ 64 <480000000>; |
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opp-peak-kBps = <800000 6451200>; |
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}; |
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cpu0_opp4: opp-576000000 { |
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opp-hz = /bits/ 64 <576000000>; |
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opp-peak-kBps = <800000 6451200>; |
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}; |
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cpu0_opp5: opp-652800000 { |
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opp-hz = /bits/ 64 <652800000>; |
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opp-peak-kBps = <800000 7680000>; |
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}; |
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cpu0_opp6: opp-748800000 { |
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opp-hz = /bits/ 64 <748800000>; |
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opp-peak-kBps = <1804000 9216000>; |
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}; |
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cpu0_opp7: opp-825600000 { |
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opp-hz = /bits/ 64 <825600000>; |
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opp-peak-kBps = <1804000 9216000>; |
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}; |
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cpu0_opp8: opp-902400000 { |
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opp-hz = /bits/ 64 <902400000>; |
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opp-peak-kBps = <1804000 10444800>; |
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}; |
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cpu0_opp9: opp-979200000 { |
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opp-hz = /bits/ 64 <979200000>; |
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opp-peak-kBps = <1804000 11980800>; |
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}; |
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cpu0_opp10: opp-1056000000 { |
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opp-hz = /bits/ 64 <1056000000>; |
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opp-peak-kBps = <1804000 11980800>; |
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}; |
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cpu0_opp11: opp-1132800000 { |
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opp-hz = /bits/ 64 <1132800000>; |
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opp-peak-kBps = <2188000 13516800>; |
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}; |
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cpu0_opp12: opp-1228800000 { |
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opp-hz = /bits/ 64 <1228800000>; |
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opp-peak-kBps = <2188000 15052800>; |
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}; |
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cpu0_opp13: opp-1324800000 { |
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opp-hz = /bits/ 64 <1324800000>; |
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opp-peak-kBps = <2188000 16588800>; |
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}; |
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|
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cpu0_opp14: opp-1420800000 { |
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opp-hz = /bits/ 64 <1420800000>; |
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opp-peak-kBps = <3072000 18124800>; |
|
}; |
|
|
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cpu0_opp15: opp-1516800000 { |
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opp-hz = /bits/ 64 <1516800000>; |
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opp-peak-kBps = <3072000 19353600>; |
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}; |
|
|
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cpu0_opp16: opp-1612800000 { |
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opp-hz = /bits/ 64 <1612800000>; |
|
opp-peak-kBps = <4068000 19353600>; |
|
}; |
|
|
|
cpu0_opp17: opp-1689600000 { |
|
opp-hz = /bits/ 64 <1689600000>; |
|
opp-peak-kBps = <4068000 20889600>; |
|
}; |
|
|
|
cpu0_opp18: opp-1766400000 { |
|
opp-hz = /bits/ 64 <1766400000>; |
|
opp-peak-kBps = <4068000 22425600>; |
|
}; |
|
}; |
|
|
|
cpu4_opp_table: cpu4_opp_table { |
|
compatible = "operating-points-v2"; |
|
opp-shared; |
|
|
|
cpu4_opp1: opp-300000000 { |
|
opp-hz = /bits/ 64 <300000000>; |
|
opp-peak-kBps = <800000 4800000>; |
|
}; |
|
|
|
cpu4_opp2: opp-403200000 { |
|
opp-hz = /bits/ 64 <403200000>; |
|
opp-peak-kBps = <800000 4800000>; |
|
}; |
|
|
|
cpu4_opp3: opp-480000000 { |
|
opp-hz = /bits/ 64 <480000000>; |
|
opp-peak-kBps = <1804000 4800000>; |
|
}; |
|
|
|
cpu4_opp4: opp-576000000 { |
|
opp-hz = /bits/ 64 <576000000>; |
|
opp-peak-kBps = <1804000 4800000>; |
|
}; |
|
|
|
cpu4_opp5: opp-652800000 { |
|
opp-hz = /bits/ 64 <652800000>; |
|
opp-peak-kBps = <1804000 4800000>; |
|
}; |
|
|
|
cpu4_opp6: opp-748800000 { |
|
opp-hz = /bits/ 64 <748800000>; |
|
opp-peak-kBps = <1804000 4800000>; |
|
}; |
|
|
|
cpu4_opp7: opp-825600000 { |
|
opp-hz = /bits/ 64 <825600000>; |
|
opp-peak-kBps = <2188000 9216000>; |
|
}; |
|
|
|
cpu4_opp8: opp-902400000 { |
|
opp-hz = /bits/ 64 <902400000>; |
|
opp-peak-kBps = <2188000 9216000>; |
|
}; |
|
|
|
cpu4_opp9: opp-979200000 { |
|
opp-hz = /bits/ 64 <979200000>; |
|
opp-peak-kBps = <2188000 9216000>; |
|
}; |
|
|
|
cpu4_opp10: opp-1056000000 { |
|
opp-hz = /bits/ 64 <1056000000>; |
|
opp-peak-kBps = <3072000 9216000>; |
|
}; |
|
|
|
cpu4_opp11: opp-1132800000 { |
|
opp-hz = /bits/ 64 <1132800000>; |
|
opp-peak-kBps = <3072000 11980800>; |
|
}; |
|
|
|
cpu4_opp12: opp-1209600000 { |
|
opp-hz = /bits/ 64 <1209600000>; |
|
opp-peak-kBps = <4068000 11980800>; |
|
}; |
|
|
|
cpu4_opp13: opp-1286400000 { |
|
opp-hz = /bits/ 64 <1286400000>; |
|
opp-peak-kBps = <4068000 11980800>; |
|
}; |
|
|
|
cpu4_opp14: opp-1363200000 { |
|
opp-hz = /bits/ 64 <1363200000>; |
|
opp-peak-kBps = <4068000 15052800>; |
|
}; |
|
|
|
cpu4_opp15: opp-1459200000 { |
|
opp-hz = /bits/ 64 <1459200000>; |
|
opp-peak-kBps = <4068000 15052800>; |
|
}; |
|
|
|
cpu4_opp16: opp-1536000000 { |
|
opp-hz = /bits/ 64 <1536000000>; |
|
opp-peak-kBps = <5412000 15052800>; |
|
}; |
|
|
|
cpu4_opp17: opp-1612800000 { |
|
opp-hz = /bits/ 64 <1612800000>; |
|
opp-peak-kBps = <5412000 15052800>; |
|
}; |
|
|
|
cpu4_opp18: opp-1689600000 { |
|
opp-hz = /bits/ 64 <1689600000>; |
|
opp-peak-kBps = <5412000 19353600>; |
|
}; |
|
|
|
cpu4_opp19: opp-1766400000 { |
|
opp-hz = /bits/ 64 <1766400000>; |
|
opp-peak-kBps = <6220000 19353600>; |
|
}; |
|
|
|
cpu4_opp20: opp-1843200000 { |
|
opp-hz = /bits/ 64 <1843200000>; |
|
opp-peak-kBps = <6220000 19353600>; |
|
}; |
|
|
|
cpu4_opp21: opp-1920000000 { |
|
opp-hz = /bits/ 64 <1920000000>; |
|
opp-peak-kBps = <7216000 19353600>; |
|
}; |
|
|
|
cpu4_opp22: opp-1996800000 { |
|
opp-hz = /bits/ 64 <1996800000>; |
|
opp-peak-kBps = <7216000 20889600>; |
|
}; |
|
|
|
cpu4_opp23: opp-2092800000 { |
|
opp-hz = /bits/ 64 <2092800000>; |
|
opp-peak-kBps = <7216000 20889600>; |
|
}; |
|
|
|
cpu4_opp24: opp-2169600000 { |
|
opp-hz = /bits/ 64 <2169600000>; |
|
opp-peak-kBps = <7216000 20889600>; |
|
}; |
|
|
|
cpu4_opp25: opp-2246400000 { |
|
opp-hz = /bits/ 64 <2246400000>; |
|
opp-peak-kBps = <7216000 20889600>; |
|
}; |
|
|
|
cpu4_opp26: opp-2323200000 { |
|
opp-hz = /bits/ 64 <2323200000>; |
|
opp-peak-kBps = <7216000 20889600>; |
|
}; |
|
|
|
cpu4_opp27: opp-2400000000 { |
|
opp-hz = /bits/ 64 <2400000000>; |
|
opp-peak-kBps = <7216000 22425600>; |
|
}; |
|
|
|
cpu4_opp28: opp-2476800000 { |
|
opp-hz = /bits/ 64 <2476800000>; |
|
opp-peak-kBps = <7216000 22425600>; |
|
}; |
|
|
|
cpu4_opp29: opp-2553600000 { |
|
opp-hz = /bits/ 64 <2553600000>; |
|
opp-peak-kBps = <7216000 22425600>; |
|
}; |
|
|
|
cpu4_opp30: opp-2649600000 { |
|
opp-hz = /bits/ 64 <2649600000>; |
|
opp-peak-kBps = <7216000 22425600>; |
|
}; |
|
|
|
cpu4_opp31: opp-2745600000 { |
|
opp-hz = /bits/ 64 <2745600000>; |
|
opp-peak-kBps = <7216000 25497600>; |
|
}; |
|
|
|
cpu4_opp32: opp-2803200000 { |
|
opp-hz = /bits/ 64 <2803200000>; |
|
opp-peak-kBps = <7216000 25497600>; |
|
}; |
|
}; |
|
|
|
pmu { |
|
compatible = "arm,armv8-pmuv3"; |
|
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
timer { |
|
compatible = "arm,armv8-timer"; |
|
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
|
<GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
|
}; |
|
|
|
clocks { |
|
xo_board: xo-board { |
|
compatible = "fixed-clock"; |
|
#clock-cells = <0>; |
|
clock-frequency = <38400000>; |
|
clock-output-names = "xo_board"; |
|
}; |
|
|
|
sleep_clk: sleep-clk { |
|
compatible = "fixed-clock"; |
|
#clock-cells = <0>; |
|
clock-frequency = <32764>; |
|
}; |
|
}; |
|
|
|
firmware { |
|
scm { |
|
compatible = "qcom,scm-sdm845", "qcom,scm"; |
|
}; |
|
}; |
|
|
|
adsp_pas: remoteproc-adsp { |
|
compatible = "qcom,sdm845-adsp-pas"; |
|
|
|
interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
memory-region = <&adsp_mem>; |
|
|
|
qcom,smem-states = <&adsp_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
status = "disabled"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; |
|
label = "lpass"; |
|
qcom,remote-pid = <2>; |
|
mboxes = <&apss_shared 8>; |
|
|
|
apr { |
|
compatible = "qcom,apr-v2"; |
|
qcom,glink-channels = "apr_audio_svc"; |
|
qcom,apr-domain = <APR_DOMAIN_ADSP>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
qcom,intents = <512 20>; |
|
|
|
apr-service@3 { |
|
reg = <APR_SVC_ADSP_CORE>; |
|
compatible = "qcom,q6core"; |
|
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
|
}; |
|
|
|
q6afe: apr-service@4 { |
|
compatible = "qcom,q6afe"; |
|
reg = <APR_SVC_AFE>; |
|
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
|
q6afedai: dais { |
|
compatible = "qcom,q6afe-dais"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#sound-dai-cells = <1>; |
|
}; |
|
}; |
|
|
|
q6asm: apr-service@7 { |
|
compatible = "qcom,q6asm"; |
|
reg = <APR_SVC_ASM>; |
|
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
|
q6asmdai: dais { |
|
compatible = "qcom,q6asm-dais"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
#sound-dai-cells = <1>; |
|
iommus = <&apps_smmu 0x1821 0x0>; |
|
}; |
|
}; |
|
|
|
q6adm: apr-service@8 { |
|
compatible = "qcom,q6adm"; |
|
reg = <APR_SVC_ADM>; |
|
qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; |
|
q6routing: routing { |
|
compatible = "qcom,q6adm-routing"; |
|
#sound-dai-cells = <0>; |
|
}; |
|
}; |
|
}; |
|
|
|
fastrpc { |
|
compatible = "qcom,fastrpc"; |
|
qcom,glink-channels = "fastrpcglink-apps-dsp"; |
|
label = "adsp"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
compute-cb@3 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <3>; |
|
iommus = <&apps_smmu 0x1823 0x0>; |
|
}; |
|
|
|
compute-cb@4 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <4>; |
|
iommus = <&apps_smmu 0x1824 0x0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
cdsp_pas: remoteproc-cdsp { |
|
compatible = "qcom,sdm845-cdsp-pas"; |
|
|
|
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "xo"; |
|
|
|
memory-region = <&cdsp_mem>; |
|
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
status = "disabled"; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; |
|
label = "turing"; |
|
qcom,remote-pid = <5>; |
|
mboxes = <&apss_shared 4>; |
|
fastrpc { |
|
compatible = "qcom,fastrpc"; |
|
qcom,glink-channels = "fastrpcglink-apps-dsp"; |
|
label = "cdsp"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
compute-cb@1 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <1>; |
|
iommus = <&apps_smmu 0x1401 0x30>; |
|
}; |
|
|
|
compute-cb@2 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <2>; |
|
iommus = <&apps_smmu 0x1402 0x30>; |
|
}; |
|
|
|
compute-cb@3 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <3>; |
|
iommus = <&apps_smmu 0x1403 0x30>; |
|
}; |
|
|
|
compute-cb@4 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <4>; |
|
iommus = <&apps_smmu 0x1404 0x30>; |
|
}; |
|
|
|
compute-cb@5 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <5>; |
|
iommus = <&apps_smmu 0x1405 0x30>; |
|
}; |
|
|
|
compute-cb@6 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <6>; |
|
iommus = <&apps_smmu 0x1406 0x30>; |
|
}; |
|
|
|
compute-cb@7 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <7>; |
|
iommus = <&apps_smmu 0x1407 0x30>; |
|
}; |
|
|
|
compute-cb@8 { |
|
compatible = "qcom,fastrpc-compute-cb"; |
|
reg = <8>; |
|
iommus = <&apps_smmu 0x1408 0x30>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
tcsr_mutex: hwlock { |
|
compatible = "qcom,tcsr-mutex"; |
|
syscon = <&tcsr_mutex_regs 0 0x1000>; |
|
#hwlock-cells = <1>; |
|
}; |
|
|
|
smem { |
|
compatible = "qcom,smem"; |
|
memory-region = <&smem_mem>; |
|
hwlocks = <&tcsr_mutex 3>; |
|
}; |
|
|
|
smp2p-cdsp { |
|
compatible = "qcom,smp2p"; |
|
qcom,smem = <94>, <432>; |
|
|
|
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; |
|
|
|
mboxes = <&apss_shared 6>; |
|
|
|
qcom,local-pid = <0>; |
|
qcom,remote-pid = <5>; |
|
|
|
cdsp_smp2p_out: master-kernel { |
|
qcom,entry-name = "master-kernel"; |
|
#qcom,smem-state-cells = <1>; |
|
}; |
|
|
|
cdsp_smp2p_in: slave-kernel { |
|
qcom,entry-name = "slave-kernel"; |
|
|
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
}; |
|
|
|
smp2p-lpass { |
|
compatible = "qcom,smp2p"; |
|
qcom,smem = <443>, <429>; |
|
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
|
|
|
mboxes = <&apss_shared 10>; |
|
|
|
qcom,local-pid = <0>; |
|
qcom,remote-pid = <2>; |
|
|
|
adsp_smp2p_out: master-kernel { |
|
qcom,entry-name = "master-kernel"; |
|
#qcom,smem-state-cells = <1>; |
|
}; |
|
|
|
adsp_smp2p_in: slave-kernel { |
|
qcom,entry-name = "slave-kernel"; |
|
|
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
}; |
|
|
|
smp2p-mpss { |
|
compatible = "qcom,smp2p"; |
|
qcom,smem = <435>, <428>; |
|
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
|
mboxes = <&apss_shared 14>; |
|
qcom,local-pid = <0>; |
|
qcom,remote-pid = <1>; |
|
|
|
modem_smp2p_out: master-kernel { |
|
qcom,entry-name = "master-kernel"; |
|
#qcom,smem-state-cells = <1>; |
|
}; |
|
|
|
modem_smp2p_in: slave-kernel { |
|
qcom,entry-name = "slave-kernel"; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
|
|
ipa_smp2p_out: ipa-ap-to-modem { |
|
qcom,entry-name = "ipa"; |
|
#qcom,smem-state-cells = <1>; |
|
}; |
|
|
|
ipa_smp2p_in: ipa-modem-to-ap { |
|
qcom,entry-name = "ipa"; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
}; |
|
|
|
smp2p-slpi { |
|
compatible = "qcom,smp2p"; |
|
qcom,smem = <481>, <430>; |
|
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; |
|
mboxes = <&apss_shared 26>; |
|
qcom,local-pid = <0>; |
|
qcom,remote-pid = <3>; |
|
|
|
slpi_smp2p_out: master-kernel { |
|
qcom,entry-name = "master-kernel"; |
|
#qcom,smem-state-cells = <1>; |
|
}; |
|
|
|
slpi_smp2p_in: slave-kernel { |
|
qcom,entry-name = "slave-kernel"; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
}; |
|
}; |
|
|
|
psci { |
|
compatible = "arm,psci-1.0"; |
|
method = "smc"; |
|
}; |
|
|
|
soc: soc@0 { |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges = <0 0 0 0 0x10 0>; |
|
dma-ranges = <0 0 0 0 0x10 0>; |
|
compatible = "simple-bus"; |
|
|
|
gcc: clock-controller@100000 { |
|
compatible = "qcom,gcc-sdm845"; |
|
reg = <0 0x00100000 0 0x1f0000>; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
qfprom@784000 { |
|
compatible = "qcom,qfprom"; |
|
reg = <0 0x00784000 0 0x8ff>; |
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
|
|
qusb2p_hstx_trim: hstx-trim-primary@1eb { |
|
reg = <0x1eb 0x1>; |
|
bits = <1 4>; |
|
}; |
|
|
|
qusb2s_hstx_trim: hstx-trim-secondary@1eb { |
|
reg = <0x1eb 0x2>; |
|
bits = <6 4>; |
|
}; |
|
}; |
|
|
|
rng: rng@793000 { |
|
compatible = "qcom,prng-ee"; |
|
reg = <0 0x00793000 0 0x1000>; |
|
clocks = <&gcc GCC_PRNG_AHB_CLK>; |
|
clock-names = "core"; |
|
}; |
|
|
|
qup_opp_table: qup-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-50000000 { |
|
opp-hz = /bits/ 64 <50000000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-75000000 { |
|
opp-hz = /bits/ 64 <75000000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-100000000 { |
|
opp-hz = /bits/ 64 <100000000>; |
|
required-opps = <&rpmhpd_opp_svs>; |
|
}; |
|
|
|
opp-128000000 { |
|
opp-hz = /bits/ 64 <128000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
}; |
|
}; |
|
|
|
qupv3_id_0: geniqup@8c0000 { |
|
compatible = "qcom,geni-se-qup"; |
|
reg = <0 0x008c0000 0 0x6000>; |
|
clock-names = "m-ahb", "s-ahb"; |
|
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
|
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
|
iommus = <&apps_smmu 0x3 0x0>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core"; |
|
status = "disabled"; |
|
|
|
i2c0: i2c@880000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00880000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c0_default>; |
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi0: spi@880000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00880000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi0_default>; |
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart0: serial@880000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00880000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart0_default>; |
|
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c1: i2c@884000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00884000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c1_default>; |
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi1: spi@884000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00884000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi1_default>; |
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart1: serial@884000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00884000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart1_default>; |
|
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c2: i2c@888000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00888000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c2_default>; |
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi2: spi@888000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00888000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi2_default>; |
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart2: serial@888000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00888000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart2_default>; |
|
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c3: i2c@88c000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x0088c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c3_default>; |
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi3: spi@88c000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x0088c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi3_default>; |
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart3: serial@88c000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x0088c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart3_default>; |
|
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c4: i2c@890000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00890000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c4_default>; |
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi4: spi@890000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00890000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi4_default>; |
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart4: serial@890000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00890000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart4_default>; |
|
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c5: i2c@894000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00894000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c5_default>; |
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi5: spi@894000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00894000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi5_default>; |
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart5: serial@894000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00894000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart5_default>; |
|
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c6: i2c@898000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00898000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c6_default>; |
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&aggre1_noc MASTER_QUP_1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi6: spi@898000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00898000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi6_default>; |
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart6: serial@898000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00898000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart6_default>; |
|
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c7: i2c@89c000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x0089c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c7_default>; |
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
status = "disabled"; |
|
}; |
|
|
|
spi7: spi@89c000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x0089c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi7_default>; |
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart7: serial@89c000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x0089c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart7_default>; |
|
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
qupv3_id_1: geniqup@ac0000 { |
|
compatible = "qcom,geni-se-qup"; |
|
reg = <0 0x00ac0000 0 0x6000>; |
|
clock-names = "m-ahb", "s-ahb"; |
|
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
|
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
|
iommus = <&apps_smmu 0x6c3 0x0>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core"; |
|
status = "disabled"; |
|
|
|
i2c8: i2c@a80000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a80000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c8_default>; |
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi8: spi@a80000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a80000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi8_default>; |
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart8: serial@a80000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a80000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart8_default>; |
|
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c9: i2c@a84000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a84000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c9_default>; |
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi9: spi@a84000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a84000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi9_default>; |
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart9: serial@a84000 { |
|
compatible = "qcom,geni-debug-uart"; |
|
reg = <0 0x00a84000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart9_default>; |
|
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c10: i2c@a88000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a88000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c10_default>; |
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi10: spi@a88000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a88000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi10_default>; |
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart10: serial@a88000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a88000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart10_default>; |
|
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c11: i2c@a8c000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a8c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c11_default>; |
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi11: spi@a8c000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a8c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi11_default>; |
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart11: serial@a8c000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a8c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart11_default>; |
|
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c12: i2c@a90000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a90000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c12_default>; |
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi12: spi@a90000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a90000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi12_default>; |
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart12: serial@a90000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a90000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart12_default>; |
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c13: i2c@a94000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a94000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c13_default>; |
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi13: spi@a94000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a94000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi13_default>; |
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart13: serial@a94000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a94000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart13_default>; |
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c14: i2c@a98000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a98000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c14_default>; |
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
status = "disabled"; |
|
}; |
|
|
|
spi14: spi@a98000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a98000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi14_default>; |
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart14: serial@a98000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a98000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart14_default>; |
|
interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
i2c15: i2c@a9c000 { |
|
compatible = "qcom,geni-i2c"; |
|
reg = <0 0x00a9c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_i2c15_default>; |
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
status = "disabled"; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&aggre2_noc MASTER_QUP_2 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "qup-core", "qup-config", "qup-memory"; |
|
}; |
|
|
|
spi15: spi@a9c000 { |
|
compatible = "qcom,geni-spi"; |
|
reg = <0 0x00a9c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_spi15_default>; |
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
|
|
uart15: serial@a9c000 { |
|
compatible = "qcom,geni-uart"; |
|
reg = <0 0x00a9c000 0 0x4000>; |
|
clock-names = "se"; |
|
clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&qup_uart15_default>; |
|
interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qup_opp_table>; |
|
interconnects = <&aggre2_noc MASTER_QUP_2 0 &config_noc SLAVE_BLSP_2 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_2 0>; |
|
interconnect-names = "qup-core", "qup-config"; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
system-cache-controller@1100000 { |
|
compatible = "qcom,sdm845-llcc"; |
|
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; |
|
reg-names = "llcc_base", "llcc_broadcast_base"; |
|
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
pcie0: pci@1c00000 { |
|
compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; |
|
reg = <0 0x01c00000 0 0x2000>, |
|
<0 0x60000000 0 0xf1d>, |
|
<0 0x60000f20 0 0xa8>, |
|
<0 0x60100000 0 0x100000>; |
|
reg-names = "parf", "dbi", "elbi", "config"; |
|
device_type = "pci"; |
|
linux,pci-domain = <0>; |
|
bus-range = <0x00 0xff>; |
|
num-lanes = <1>; |
|
|
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
|
|
ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>, |
|
<0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>; |
|
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "msi"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0x7>; |
|
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
|
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
|
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
|
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
|
|
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, |
|
<&gcc GCC_PCIE_0_AUX_CLK>, |
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
|
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>, |
|
<&gcc GCC_PCIE_0_SLV_AXI_CLK>, |
|
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, |
|
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; |
|
clock-names = "pipe", |
|
"aux", |
|
"cfg", |
|
"bus_master", |
|
"bus_slave", |
|
"slave_q2a", |
|
"tbu"; |
|
|
|
iommus = <&apps_smmu 0x1c10 0xf>; |
|
iommu-map = <0x0 &apps_smmu 0x1c10 0x1>, |
|
<0x100 &apps_smmu 0x1c11 0x1>, |
|
<0x200 &apps_smmu 0x1c12 0x1>, |
|
<0x300 &apps_smmu 0x1c13 0x1>, |
|
<0x400 &apps_smmu 0x1c14 0x1>, |
|
<0x500 &apps_smmu 0x1c15 0x1>, |
|
<0x600 &apps_smmu 0x1c16 0x1>, |
|
<0x700 &apps_smmu 0x1c17 0x1>, |
|
<0x800 &apps_smmu 0x1c18 0x1>, |
|
<0x900 &apps_smmu 0x1c19 0x1>, |
|
<0xa00 &apps_smmu 0x1c1a 0x1>, |
|
<0xb00 &apps_smmu 0x1c1b 0x1>, |
|
<0xc00 &apps_smmu 0x1c1c 0x1>, |
|
<0xd00 &apps_smmu 0x1c1d 0x1>, |
|
<0xe00 &apps_smmu 0x1c1e 0x1>, |
|
<0xf00 &apps_smmu 0x1c1f 0x1>; |
|
|
|
resets = <&gcc GCC_PCIE_0_BCR>; |
|
reset-names = "pci"; |
|
|
|
power-domains = <&gcc PCIE_0_GDSC>; |
|
|
|
phys = <&pcie0_lane>; |
|
phy-names = "pciephy"; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
pcie0_phy: phy@1c06000 { |
|
compatible = "qcom,sdm845-qmp-pcie-phy"; |
|
reg = <0 0x01c06000 0 0x18c>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
|
<&gcc GCC_PCIE_0_CFG_AHB_CLK>, |
|
<&gcc GCC_PCIE_0_CLKREF_CLK>, |
|
<&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
|
clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
|
|
|
resets = <&gcc GCC_PCIE_0_PHY_BCR>; |
|
reset-names = "phy"; |
|
|
|
assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
|
assigned-clock-rates = <100000000>; |
|
|
|
status = "disabled"; |
|
|
|
pcie0_lane: lanes@1c06200 { |
|
reg = <0 0x01c06200 0 0x128>, |
|
<0 0x01c06400 0 0x1fc>, |
|
<0 0x01c06800 0 0x218>, |
|
<0 0x01c06600 0 0x70>; |
|
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
|
|
#phy-cells = <0>; |
|
clock-output-names = "pcie_0_pipe_clk"; |
|
}; |
|
}; |
|
|
|
pcie1: pci@1c08000 { |
|
compatible = "qcom,pcie-sdm845", "snps,dw-pcie"; |
|
reg = <0 0x01c08000 0 0x2000>, |
|
<0 0x40000000 0 0xf1d>, |
|
<0 0x40000f20 0 0xa8>, |
|
<0 0x40100000 0 0x100000>; |
|
reg-names = "parf", "dbi", "elbi", "config"; |
|
device_type = "pci"; |
|
linux,pci-domain = <1>; |
|
bus-range = <0x00 0xff>; |
|
num-lanes = <1>; |
|
|
|
#address-cells = <3>; |
|
#size-cells = <2>; |
|
|
|
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>, |
|
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; |
|
|
|
interrupts = <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "msi"; |
|
#interrupt-cells = <1>; |
|
interrupt-map-mask = <0 0 0 0x7>; |
|
interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ |
|
<0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ |
|
<0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ |
|
<0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ |
|
|
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, |
|
<&gcc GCC_PCIE_1_AUX_CLK>, |
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
|
<&gcc GCC_PCIE_1_MSTR_AXI_CLK>, |
|
<&gcc GCC_PCIE_1_SLV_AXI_CLK>, |
|
<&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, |
|
<&gcc GCC_PCIE_1_CLKREF_CLK>, |
|
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>; |
|
clock-names = "pipe", |
|
"aux", |
|
"cfg", |
|
"bus_master", |
|
"bus_slave", |
|
"slave_q2a", |
|
"ref", |
|
"tbu"; |
|
|
|
assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; |
|
assigned-clock-rates = <19200000>; |
|
|
|
iommus = <&apps_smmu 0x1c00 0xf>; |
|
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, |
|
<0x100 &apps_smmu 0x1c01 0x1>, |
|
<0x200 &apps_smmu 0x1c02 0x1>, |
|
<0x300 &apps_smmu 0x1c03 0x1>, |
|
<0x400 &apps_smmu 0x1c04 0x1>, |
|
<0x500 &apps_smmu 0x1c05 0x1>, |
|
<0x600 &apps_smmu 0x1c06 0x1>, |
|
<0x700 &apps_smmu 0x1c07 0x1>, |
|
<0x800 &apps_smmu 0x1c08 0x1>, |
|
<0x900 &apps_smmu 0x1c09 0x1>, |
|
<0xa00 &apps_smmu 0x1c0a 0x1>, |
|
<0xb00 &apps_smmu 0x1c0b 0x1>, |
|
<0xc00 &apps_smmu 0x1c0c 0x1>, |
|
<0xd00 &apps_smmu 0x1c0d 0x1>, |
|
<0xe00 &apps_smmu 0x1c0e 0x1>, |
|
<0xf00 &apps_smmu 0x1c0f 0x1>; |
|
|
|
resets = <&gcc GCC_PCIE_1_BCR>; |
|
reset-names = "pci"; |
|
|
|
power-domains = <&gcc PCIE_1_GDSC>; |
|
|
|
phys = <&pcie1_lane>; |
|
phy-names = "pciephy"; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
pcie1_phy: phy@1c0a000 { |
|
compatible = "qcom,sdm845-qhp-pcie-phy"; |
|
reg = <0 0x01c0a000 0 0x800>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
|
<&gcc GCC_PCIE_1_CFG_AHB_CLK>, |
|
<&gcc GCC_PCIE_1_CLKREF_CLK>, |
|
<&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
|
clock-names = "aux", "cfg_ahb", "ref", "refgen"; |
|
|
|
resets = <&gcc GCC_PCIE_1_PHY_BCR>; |
|
reset-names = "phy"; |
|
|
|
assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>; |
|
assigned-clock-rates = <100000000>; |
|
|
|
status = "disabled"; |
|
|
|
pcie1_lane: lanes@1c06200 { |
|
reg = <0 0x01c0a800 0 0x800>, |
|
<0 0x01c0a800 0 0x800>, |
|
<0 0x01c0b800 0 0x400>; |
|
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
|
|
#phy-cells = <0>; |
|
clock-output-names = "pcie_1_pipe_clk"; |
|
}; |
|
}; |
|
|
|
mem_noc: interconnect@1380000 { |
|
compatible = "qcom,sdm845-mem-noc"; |
|
reg = <0 0x01380000 0 0x27200>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
dc_noc: interconnect@14e0000 { |
|
compatible = "qcom,sdm845-dc-noc"; |
|
reg = <0 0x014e0000 0 0x400>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
config_noc: interconnect@1500000 { |
|
compatible = "qcom,sdm845-config-noc"; |
|
reg = <0 0x01500000 0 0x5080>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
system_noc: interconnect@1620000 { |
|
compatible = "qcom,sdm845-system-noc"; |
|
reg = <0 0x01620000 0 0x18080>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre1_noc: interconnect@16e0000 { |
|
compatible = "qcom,sdm845-aggre1-noc"; |
|
reg = <0 0x016e0000 0 0x15080>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
aggre2_noc: interconnect@1700000 { |
|
compatible = "qcom,sdm845-aggre2-noc"; |
|
reg = <0 0x01700000 0 0x1f300>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
mmss_noc: interconnect@1740000 { |
|
compatible = "qcom,sdm845-mmss-noc"; |
|
reg = <0 0x01740000 0 0x1c100>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
ufs_mem_hc: ufshc@1d84000 { |
|
compatible = "qcom,sdm845-ufshc", "qcom,ufshc", |
|
"jedec,ufs-2.0"; |
|
reg = <0 0x01d84000 0 0x2500>, |
|
<0 0x01d90000 0 0x8000>; |
|
reg-names = "std", "ice"; |
|
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
|
phys = <&ufs_mem_phy_lanes>; |
|
phy-names = "ufsphy"; |
|
lanes-per-direction = <2>; |
|
power-domains = <&gcc UFS_PHY_GDSC>; |
|
#reset-cells = <1>; |
|
resets = <&gcc GCC_UFS_PHY_BCR>; |
|
reset-names = "rst"; |
|
|
|
iommus = <&apps_smmu 0x100 0xf>; |
|
|
|
clock-names = |
|
"core_clk", |
|
"bus_aggr_clk", |
|
"iface_clk", |
|
"core_clk_unipro", |
|
"ref_clk", |
|
"tx_lane0_sync_clk", |
|
"rx_lane0_sync_clk", |
|
"rx_lane1_sync_clk", |
|
"ice_core_clk"; |
|
clocks = |
|
<&gcc GCC_UFS_PHY_AXI_CLK>, |
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
|
<&gcc GCC_UFS_PHY_AHB_CLK>, |
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, |
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>; |
|
freq-table-hz = |
|
<50000000 200000000>, |
|
<0 0>, |
|
<0 0>, |
|
<37500000 150000000>, |
|
<0 0>, |
|
<0 0>, |
|
<0 0>, |
|
<0 0>, |
|
<0 300000000>; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
ufs_mem_phy: phy@1d87000 { |
|
compatible = "qcom,sdm845-qmp-ufs-phy"; |
|
reg = <0 0x01d87000 0 0x18c>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
clock-names = "ref", |
|
"ref_aux"; |
|
clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, |
|
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
|
|
|
resets = <&ufs_mem_hc 0>; |
|
reset-names = "ufsphy"; |
|
status = "disabled"; |
|
|
|
ufs_mem_phy_lanes: lanes@1d87400 { |
|
reg = <0 0x01d87400 0 0x108>, |
|
<0 0x01d87600 0 0x1e0>, |
|
<0 0x01d87c00 0 0x1dc>, |
|
<0 0x01d87800 0 0x108>, |
|
<0 0x01d87a00 0 0x1e0>; |
|
#phy-cells = <0>; |
|
}; |
|
}; |
|
|
|
cryptobam: dma@1dc4000 { |
|
compatible = "qcom,bam-v1.7.0"; |
|
reg = <0 0x01dc4000 0 0x24000>; |
|
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&rpmhcc 15>; |
|
clock-names = "bam_clk"; |
|
#dma-cells = <1>; |
|
qcom,ee = <0>; |
|
qcom,controlled-remotely = <1>; |
|
iommus = <&apps_smmu 0x704 0x1>, |
|
<&apps_smmu 0x706 0x1>, |
|
<&apps_smmu 0x714 0x1>, |
|
<&apps_smmu 0x716 0x1>; |
|
}; |
|
|
|
crypto: crypto@1dfa000 { |
|
compatible = "qcom,crypto-v5.4"; |
|
reg = <0 0x01dfa000 0 0x6000>; |
|
clocks = <&gcc GCC_CE1_AHB_CLK>, |
|
<&gcc GCC_CE1_AHB_CLK>, |
|
<&rpmhcc 15>; |
|
clock-names = "iface", "bus", "core"; |
|
dmas = <&cryptobam 6>, <&cryptobam 7>; |
|
dma-names = "rx", "tx"; |
|
iommus = <&apps_smmu 0x704 0x1>, |
|
<&apps_smmu 0x706 0x1>, |
|
<&apps_smmu 0x714 0x1>, |
|
<&apps_smmu 0x716 0x1>; |
|
}; |
|
|
|
ipa: ipa@1e40000 { |
|
compatible = "qcom,sdm845-ipa"; |
|
|
|
iommus = <&apps_smmu 0x720 0x0>, |
|
<&apps_smmu 0x722 0x0>; |
|
reg = <0 0x1e40000 0 0x7000>, |
|
<0 0x1e47000 0 0x2000>, |
|
<0 0x1e04000 0 0x2c000>; |
|
reg-names = "ipa-reg", |
|
"ipa-shared", |
|
"gsi"; |
|
|
|
interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>, |
|
<&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, |
|
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "ipa", |
|
"gsi", |
|
"ipa-clock-query", |
|
"ipa-setup-ready"; |
|
|
|
clocks = <&rpmhcc RPMH_IPA_CLK>; |
|
clock-names = "core"; |
|
|
|
interconnects = <&aggre2_noc MASTER_IPA 0 &mem_noc SLAVE_EBI1 0>, |
|
<&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; |
|
interconnect-names = "memory", |
|
"imem", |
|
"config"; |
|
|
|
qcom,smem-states = <&ipa_smp2p_out 0>, |
|
<&ipa_smp2p_out 1>; |
|
qcom,smem-state-names = "ipa-clock-enabled-valid", |
|
"ipa-clock-enabled"; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
tcsr_mutex_regs: syscon@1f40000 { |
|
compatible = "syscon"; |
|
reg = <0 0x01f40000 0 0x40000>; |
|
}; |
|
|
|
tlmm: pinctrl@3400000 { |
|
compatible = "qcom,sdm845-pinctrl"; |
|
reg = <0 0x03400000 0 0xc00000>; |
|
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
interrupt-controller; |
|
#interrupt-cells = <2>; |
|
gpio-ranges = <&tlmm 0 0 151>; |
|
wakeup-parent = <&pdc_intc>; |
|
|
|
cci0_default: cci0-default { |
|
/* SDA, SCL */ |
|
pins = "gpio17", "gpio18"; |
|
function = "cci_i2c"; |
|
|
|
bias-pull-up; |
|
drive-strength = <2>; /* 2 mA */ |
|
}; |
|
|
|
cci0_sleep: cci0-sleep { |
|
/* SDA, SCL */ |
|
pins = "gpio17", "gpio18"; |
|
function = "cci_i2c"; |
|
|
|
drive-strength = <2>; /* 2 mA */ |
|
bias-pull-down; |
|
}; |
|
|
|
cci1_default: cci1-default { |
|
/* SDA, SCL */ |
|
pins = "gpio19", "gpio20"; |
|
function = "cci_i2c"; |
|
|
|
bias-pull-up; |
|
drive-strength = <2>; /* 2 mA */ |
|
}; |
|
|
|
cci1_sleep: cci1-sleep { |
|
/* SDA, SCL */ |
|
pins = "gpio19", "gpio20"; |
|
function = "cci_i2c"; |
|
|
|
drive-strength = <2>; /* 2 mA */ |
|
bias-pull-down; |
|
}; |
|
|
|
qspi_clk: qspi-clk { |
|
pinmux { |
|
pins = "gpio95"; |
|
function = "qspi_clk"; |
|
}; |
|
}; |
|
|
|
qspi_cs0: qspi-cs0 { |
|
pinmux { |
|
pins = "gpio90"; |
|
function = "qspi_cs"; |
|
}; |
|
}; |
|
|
|
qspi_cs1: qspi-cs1 { |
|
pinmux { |
|
pins = "gpio89"; |
|
function = "qspi_cs"; |
|
}; |
|
}; |
|
|
|
qspi_data01: qspi-data01 { |
|
pinmux-data { |
|
pins = "gpio91", "gpio92"; |
|
function = "qspi_data"; |
|
}; |
|
}; |
|
|
|
qspi_data12: qspi-data12 { |
|
pinmux-data { |
|
pins = "gpio93", "gpio94"; |
|
function = "qspi_data"; |
|
}; |
|
}; |
|
|
|
qup_i2c0_default: qup-i2c0-default { |
|
pinmux { |
|
pins = "gpio0", "gpio1"; |
|
function = "qup0"; |
|
}; |
|
}; |
|
|
|
qup_i2c1_default: qup-i2c1-default { |
|
pinmux { |
|
pins = "gpio17", "gpio18"; |
|
function = "qup1"; |
|
}; |
|
}; |
|
|
|
qup_i2c2_default: qup-i2c2-default { |
|
pinmux { |
|
pins = "gpio27", "gpio28"; |
|
function = "qup2"; |
|
}; |
|
}; |
|
|
|
qup_i2c3_default: qup-i2c3-default { |
|
pinmux { |
|
pins = "gpio41", "gpio42"; |
|
function = "qup3"; |
|
}; |
|
}; |
|
|
|
qup_i2c4_default: qup-i2c4-default { |
|
pinmux { |
|
pins = "gpio89", "gpio90"; |
|
function = "qup4"; |
|
}; |
|
}; |
|
|
|
qup_i2c5_default: qup-i2c5-default { |
|
pinmux { |
|
pins = "gpio85", "gpio86"; |
|
function = "qup5"; |
|
}; |
|
}; |
|
|
|
qup_i2c6_default: qup-i2c6-default { |
|
pinmux { |
|
pins = "gpio45", "gpio46"; |
|
function = "qup6"; |
|
}; |
|
}; |
|
|
|
qup_i2c7_default: qup-i2c7-default { |
|
pinmux { |
|
pins = "gpio93", "gpio94"; |
|
function = "qup7"; |
|
}; |
|
}; |
|
|
|
qup_i2c8_default: qup-i2c8-default { |
|
pinmux { |
|
pins = "gpio65", "gpio66"; |
|
function = "qup8"; |
|
}; |
|
}; |
|
|
|
qup_i2c9_default: qup-i2c9-default { |
|
pinmux { |
|
pins = "gpio6", "gpio7"; |
|
function = "qup9"; |
|
}; |
|
}; |
|
|
|
qup_i2c10_default: qup-i2c10-default { |
|
pinmux { |
|
pins = "gpio55", "gpio56"; |
|
function = "qup10"; |
|
}; |
|
}; |
|
|
|
qup_i2c11_default: qup-i2c11-default { |
|
pinmux { |
|
pins = "gpio31", "gpio32"; |
|
function = "qup11"; |
|
}; |
|
}; |
|
|
|
qup_i2c12_default: qup-i2c12-default { |
|
pinmux { |
|
pins = "gpio49", "gpio50"; |
|
function = "qup12"; |
|
}; |
|
}; |
|
|
|
qup_i2c13_default: qup-i2c13-default { |
|
pinmux { |
|
pins = "gpio105", "gpio106"; |
|
function = "qup13"; |
|
}; |
|
}; |
|
|
|
qup_i2c14_default: qup-i2c14-default { |
|
pinmux { |
|
pins = "gpio33", "gpio34"; |
|
function = "qup14"; |
|
}; |
|
}; |
|
|
|
qup_i2c15_default: qup-i2c15-default { |
|
pinmux { |
|
pins = "gpio81", "gpio82"; |
|
function = "qup15"; |
|
}; |
|
}; |
|
|
|
qup_spi0_default: qup-spi0-default { |
|
pinmux { |
|
pins = "gpio0", "gpio1", |
|
"gpio2", "gpio3"; |
|
function = "qup0"; |
|
}; |
|
}; |
|
|
|
qup_spi1_default: qup-spi1-default { |
|
pinmux { |
|
pins = "gpio17", "gpio18", |
|
"gpio19", "gpio20"; |
|
function = "qup1"; |
|
}; |
|
}; |
|
|
|
qup_spi2_default: qup-spi2-default { |
|
pinmux { |
|
pins = "gpio27", "gpio28", |
|
"gpio29", "gpio30"; |
|
function = "qup2"; |
|
}; |
|
}; |
|
|
|
qup_spi3_default: qup-spi3-default { |
|
pinmux { |
|
pins = "gpio41", "gpio42", |
|
"gpio43", "gpio44"; |
|
function = "qup3"; |
|
}; |
|
}; |
|
|
|
qup_spi4_default: qup-spi4-default { |
|
pinmux { |
|
pins = "gpio89", "gpio90", |
|
"gpio91", "gpio92"; |
|
function = "qup4"; |
|
}; |
|
}; |
|
|
|
qup_spi5_default: qup-spi5-default { |
|
pinmux { |
|
pins = "gpio85", "gpio86", |
|
"gpio87", "gpio88"; |
|
function = "qup5"; |
|
}; |
|
}; |
|
|
|
qup_spi6_default: qup-spi6-default { |
|
pinmux { |
|
pins = "gpio45", "gpio46", |
|
"gpio47", "gpio48"; |
|
function = "qup6"; |
|
}; |
|
}; |
|
|
|
qup_spi7_default: qup-spi7-default { |
|
pinmux { |
|
pins = "gpio93", "gpio94", |
|
"gpio95", "gpio96"; |
|
function = "qup7"; |
|
}; |
|
}; |
|
|
|
qup_spi8_default: qup-spi8-default { |
|
pinmux { |
|
pins = "gpio65", "gpio66", |
|
"gpio67", "gpio68"; |
|
function = "qup8"; |
|
}; |
|
}; |
|
|
|
qup_spi9_default: qup-spi9-default { |
|
pinmux { |
|
pins = "gpio6", "gpio7", |
|
"gpio4", "gpio5"; |
|
function = "qup9"; |
|
}; |
|
}; |
|
|
|
qup_spi10_default: qup-spi10-default { |
|
pinmux { |
|
pins = "gpio55", "gpio56", |
|
"gpio53", "gpio54"; |
|
function = "qup10"; |
|
}; |
|
}; |
|
|
|
qup_spi11_default: qup-spi11-default { |
|
pinmux { |
|
pins = "gpio31", "gpio32", |
|
"gpio33", "gpio34"; |
|
function = "qup11"; |
|
}; |
|
}; |
|
|
|
qup_spi12_default: qup-spi12-default { |
|
pinmux { |
|
pins = "gpio49", "gpio50", |
|
"gpio51", "gpio52"; |
|
function = "qup12"; |
|
}; |
|
}; |
|
|
|
qup_spi13_default: qup-spi13-default { |
|
pinmux { |
|
pins = "gpio105", "gpio106", |
|
"gpio107", "gpio108"; |
|
function = "qup13"; |
|
}; |
|
}; |
|
|
|
qup_spi14_default: qup-spi14-default { |
|
pinmux { |
|
pins = "gpio33", "gpio34", |
|
"gpio31", "gpio32"; |
|
function = "qup14"; |
|
}; |
|
}; |
|
|
|
qup_spi15_default: qup-spi15-default { |
|
pinmux { |
|
pins = "gpio81", "gpio82", |
|
"gpio83", "gpio84"; |
|
function = "qup15"; |
|
}; |
|
}; |
|
|
|
qup_uart0_default: qup-uart0-default { |
|
pinmux { |
|
pins = "gpio2", "gpio3"; |
|
function = "qup0"; |
|
}; |
|
}; |
|
|
|
qup_uart1_default: qup-uart1-default { |
|
pinmux { |
|
pins = "gpio19", "gpio20"; |
|
function = "qup1"; |
|
}; |
|
}; |
|
|
|
qup_uart2_default: qup-uart2-default { |
|
pinmux { |
|
pins = "gpio29", "gpio30"; |
|
function = "qup2"; |
|
}; |
|
}; |
|
|
|
qup_uart3_default: qup-uart3-default { |
|
pinmux { |
|
pins = "gpio43", "gpio44"; |
|
function = "qup3"; |
|
}; |
|
}; |
|
|
|
qup_uart4_default: qup-uart4-default { |
|
pinmux { |
|
pins = "gpio91", "gpio92"; |
|
function = "qup4"; |
|
}; |
|
}; |
|
|
|
qup_uart5_default: qup-uart5-default { |
|
pinmux { |
|
pins = "gpio87", "gpio88"; |
|
function = "qup5"; |
|
}; |
|
}; |
|
|
|
qup_uart6_default: qup-uart6-default { |
|
pinmux { |
|
pins = "gpio47", "gpio48"; |
|
function = "qup6"; |
|
}; |
|
}; |
|
|
|
qup_uart7_default: qup-uart7-default { |
|
pinmux { |
|
pins = "gpio95", "gpio96"; |
|
function = "qup7"; |
|
}; |
|
}; |
|
|
|
qup_uart8_default: qup-uart8-default { |
|
pinmux { |
|
pins = "gpio67", "gpio68"; |
|
function = "qup8"; |
|
}; |
|
}; |
|
|
|
qup_uart9_default: qup-uart9-default { |
|
pinmux { |
|
pins = "gpio4", "gpio5"; |
|
function = "qup9"; |
|
}; |
|
}; |
|
|
|
qup_uart10_default: qup-uart10-default { |
|
pinmux { |
|
pins = "gpio53", "gpio54"; |
|
function = "qup10"; |
|
}; |
|
}; |
|
|
|
qup_uart11_default: qup-uart11-default { |
|
pinmux { |
|
pins = "gpio33", "gpio34"; |
|
function = "qup11"; |
|
}; |
|
}; |
|
|
|
qup_uart12_default: qup-uart12-default { |
|
pinmux { |
|
pins = "gpio51", "gpio52"; |
|
function = "qup12"; |
|
}; |
|
}; |
|
|
|
qup_uart13_default: qup-uart13-default { |
|
pinmux { |
|
pins = "gpio107", "gpio108"; |
|
function = "qup13"; |
|
}; |
|
}; |
|
|
|
qup_uart14_default: qup-uart14-default { |
|
pinmux { |
|
pins = "gpio31", "gpio32"; |
|
function = "qup14"; |
|
}; |
|
}; |
|
|
|
qup_uart15_default: qup-uart15-default { |
|
pinmux { |
|
pins = "gpio83", "gpio84"; |
|
function = "qup15"; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sleep: quat_mi2s_sleep { |
|
mux { |
|
pins = "gpio58", "gpio59"; |
|
function = "gpio"; |
|
}; |
|
|
|
config { |
|
pins = "gpio58", "gpio59"; |
|
drive-strength = <2>; |
|
bias-pull-down; |
|
input-enable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_active: quat_mi2s_active { |
|
mux { |
|
pins = "gpio58", "gpio59"; |
|
function = "qua_mi2s"; |
|
}; |
|
|
|
config { |
|
pins = "gpio58", "gpio59"; |
|
drive-strength = <8>; |
|
bias-disable; |
|
output-high; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd0_sleep: quat_mi2s_sd0_sleep { |
|
mux { |
|
pins = "gpio60"; |
|
function = "gpio"; |
|
}; |
|
|
|
config { |
|
pins = "gpio60"; |
|
drive-strength = <2>; |
|
bias-pull-down; |
|
input-enable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd0_active: quat_mi2s_sd0_active { |
|
mux { |
|
pins = "gpio60"; |
|
function = "qua_mi2s"; |
|
}; |
|
|
|
config { |
|
pins = "gpio60"; |
|
drive-strength = <8>; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd1_sleep: quat_mi2s_sd1_sleep { |
|
mux { |
|
pins = "gpio61"; |
|
function = "gpio"; |
|
}; |
|
|
|
config { |
|
pins = "gpio61"; |
|
drive-strength = <2>; |
|
bias-pull-down; |
|
input-enable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd1_active: quat_mi2s_sd1_active { |
|
mux { |
|
pins = "gpio61"; |
|
function = "qua_mi2s"; |
|
}; |
|
|
|
config { |
|
pins = "gpio61"; |
|
drive-strength = <8>; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd2_sleep: quat_mi2s_sd2_sleep { |
|
mux { |
|
pins = "gpio62"; |
|
function = "gpio"; |
|
}; |
|
|
|
config { |
|
pins = "gpio62"; |
|
drive-strength = <2>; |
|
bias-pull-down; |
|
input-enable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd2_active: quat_mi2s_sd2_active { |
|
mux { |
|
pins = "gpio62"; |
|
function = "qua_mi2s"; |
|
}; |
|
|
|
config { |
|
pins = "gpio62"; |
|
drive-strength = <8>; |
|
bias-disable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd3_sleep: quat_mi2s_sd3_sleep { |
|
mux { |
|
pins = "gpio63"; |
|
function = "gpio"; |
|
}; |
|
|
|
config { |
|
pins = "gpio63"; |
|
drive-strength = <2>; |
|
bias-pull-down; |
|
input-enable; |
|
}; |
|
}; |
|
|
|
quat_mi2s_sd3_active: quat_mi2s_sd3_active { |
|
mux { |
|
pins = "gpio63"; |
|
function = "qua_mi2s"; |
|
}; |
|
|
|
config { |
|
pins = "gpio63"; |
|
drive-strength = <8>; |
|
bias-disable; |
|
}; |
|
}; |
|
}; |
|
|
|
mss_pil: remoteproc@4080000 { |
|
compatible = "qcom,sdm845-mss-pil"; |
|
reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; |
|
reg-names = "qdsp6", "rmb"; |
|
|
|
interrupts-extended = |
|
<&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, |
|
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; |
|
interrupt-names = "wdog", "fatal", "ready", |
|
"handover", "stop-ack", |
|
"shutdown-ack"; |
|
|
|
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, |
|
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, |
|
<&gcc GCC_BOOT_ROM_AHB_CLK>, |
|
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, |
|
<&gcc GCC_MSS_SNOC_AXI_CLK>, |
|
<&gcc GCC_MSS_MFAB_AXIS_CLK>, |
|
<&gcc GCC_PRNG_AHB_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "iface", "bus", "mem", "gpll0_mss", |
|
"snoc_axi", "mnoc_axi", "prng", "xo"; |
|
|
|
qcom,smem-states = <&modem_smp2p_out 0>; |
|
qcom,smem-state-names = "stop"; |
|
|
|
resets = <&aoss_reset AOSS_CC_MSS_RESTART>, |
|
<&pdc_reset PDC_MODEM_SYNC_RESET>; |
|
reset-names = "mss_restart", "pdc_reset"; |
|
|
|
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; |
|
|
|
power-domains = <&aoss_qmp 2>, |
|
<&rpmhpd SDM845_CX>, |
|
<&rpmhpd SDM845_MX>, |
|
<&rpmhpd SDM845_MSS>; |
|
power-domain-names = "load_state", "cx", "mx", "mss"; |
|
|
|
mba { |
|
memory-region = <&mba_region>; |
|
}; |
|
|
|
mpss { |
|
memory-region = <&mpss_region>; |
|
}; |
|
|
|
glink-edge { |
|
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; |
|
label = "modem"; |
|
qcom,remote-pid = <1>; |
|
mboxes = <&apss_shared 12>; |
|
}; |
|
}; |
|
|
|
gpucc: clock-controller@5090000 { |
|
compatible = "qcom,sdm845-gpucc"; |
|
reg = <0 0x05090000 0 0x9000>; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_GPU_GPLL0_CLK_SRC>, |
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
|
clock-names = "bi_tcxo", |
|
"gcc_gpu_gpll0_clk_src", |
|
"gcc_gpu_gpll0_div_clk_src"; |
|
}; |
|
|
|
stm@6002000 { |
|
compatible = "arm,coresight-stm", "arm,primecell"; |
|
reg = <0 0x06002000 0 0x1000>, |
|
<0 0x16280000 0 0x180000>; |
|
reg-names = "stm-base", "stm-stimulus-base"; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
stm_out: endpoint { |
|
remote-endpoint = |
|
<&funnel0_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6041000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06041000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel0_out: endpoint { |
|
remote-endpoint = |
|
<&merge_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@7 { |
|
reg = <7>; |
|
funnel0_in7: endpoint { |
|
remote-endpoint = <&stm_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6043000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06043000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
funnel2_out: endpoint { |
|
remote-endpoint = |
|
<&merge_funnel_in2>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@5 { |
|
reg = <5>; |
|
funnel2_in5: endpoint { |
|
remote-endpoint = |
|
<&apss_merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@6045000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x06045000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
merge_funnel_out: endpoint { |
|
remote-endpoint = <&etf_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
merge_funnel_in0: endpoint { |
|
remote-endpoint = |
|
<&funnel0_out>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <2>; |
|
merge_funnel_in2: endpoint { |
|
remote-endpoint = |
|
<&funnel2_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
replicator@6046000 { |
|
compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; |
|
reg = <0 0x06046000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
replicator_out: endpoint { |
|
remote-endpoint = <&etr_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
replicator_in: endpoint { |
|
remote-endpoint = <&etf_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etf@6047000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06047000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
etf_out: endpoint { |
|
remote-endpoint = |
|
<&replicator_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@1 { |
|
reg = <1>; |
|
etf_in: endpoint { |
|
remote-endpoint = |
|
<&merge_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etr@6048000 { |
|
compatible = "arm,coresight-tmc", "arm,primecell"; |
|
reg = <0 0x06048000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,scatter-gather; |
|
|
|
in-ports { |
|
port { |
|
etr_in: endpoint { |
|
remote-endpoint = |
|
<&replicator_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7040000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07040000 0 0x1000>; |
|
|
|
cpu = <&CPU0>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm0_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in0>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7140000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07140000 0 0x1000>; |
|
|
|
cpu = <&CPU1>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm1_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7240000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07240000 0 0x1000>; |
|
|
|
cpu = <&CPU2>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm2_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in2>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7340000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07340000 0 0x1000>; |
|
|
|
cpu = <&CPU3>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm3_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in3>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7440000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07440000 0 0x1000>; |
|
|
|
cpu = <&CPU4>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm4_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in4>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7540000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07540000 0 0x1000>; |
|
|
|
cpu = <&CPU5>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm5_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in5>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7640000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07640000 0 0x1000>; |
|
|
|
cpu = <&CPU6>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm6_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in6>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
etm@7740000 { |
|
compatible = "arm,coresight-etm4x", "arm,primecell"; |
|
reg = <0 0x07740000 0 0x1000>; |
|
|
|
cpu = <&CPU7>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
arm,coresight-loses-context-with-cpu; |
|
|
|
out-ports { |
|
port { |
|
etm7_out: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_in7>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7800000 { /* APSS Funnel */ |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07800000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_funnel_out: endpoint { |
|
remote-endpoint = |
|
<&apss_merge_funnel_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
apss_funnel_in0: endpoint { |
|
remote-endpoint = |
|
<&etm0_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
apss_funnel_in1: endpoint { |
|
remote-endpoint = |
|
<&etm1_out>; |
|
}; |
|
}; |
|
|
|
port@2 { |
|
reg = <2>; |
|
apss_funnel_in2: endpoint { |
|
remote-endpoint = |
|
<&etm2_out>; |
|
}; |
|
}; |
|
|
|
port@3 { |
|
reg = <3>; |
|
apss_funnel_in3: endpoint { |
|
remote-endpoint = |
|
<&etm3_out>; |
|
}; |
|
}; |
|
|
|
port@4 { |
|
reg = <4>; |
|
apss_funnel_in4: endpoint { |
|
remote-endpoint = |
|
<&etm4_out>; |
|
}; |
|
}; |
|
|
|
port@5 { |
|
reg = <5>; |
|
apss_funnel_in5: endpoint { |
|
remote-endpoint = |
|
<&etm5_out>; |
|
}; |
|
}; |
|
|
|
port@6 { |
|
reg = <6>; |
|
apss_funnel_in6: endpoint { |
|
remote-endpoint = |
|
<&etm6_out>; |
|
}; |
|
}; |
|
|
|
port@7 { |
|
reg = <7>; |
|
apss_funnel_in7: endpoint { |
|
remote-endpoint = |
|
<&etm7_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
funnel@7810000 { |
|
compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; |
|
reg = <0 0x07810000 0 0x1000>; |
|
|
|
clocks = <&aoss_qmp>; |
|
clock-names = "apb_pclk"; |
|
|
|
out-ports { |
|
port { |
|
apss_merge_funnel_out: endpoint { |
|
remote-endpoint = |
|
<&funnel2_in5>; |
|
}; |
|
}; |
|
}; |
|
|
|
in-ports { |
|
port { |
|
apss_merge_funnel_in: endpoint { |
|
remote-endpoint = |
|
<&apss_funnel_out>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
sdhc_2: sdhci@8804000 { |
|
compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; |
|
reg = <0 0x08804000 0 0x1000>; |
|
|
|
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hc_irq", "pwr_irq"; |
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
|
<&gcc GCC_SDCC2_APPS_CLK>; |
|
clock-names = "iface", "core"; |
|
iommus = <&apps_smmu 0xa0 0xf>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&sdhc2_opp_table>; |
|
|
|
status = "disabled"; |
|
|
|
sdhc2_opp_table: sdhc2-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-9600000 { |
|
opp-hz = /bits/ 64 <9600000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-19200000 { |
|
opp-hz = /bits/ 64 <19200000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-100000000 { |
|
opp-hz = /bits/ 64 <100000000>; |
|
required-opps = <&rpmhpd_opp_svs>; |
|
}; |
|
|
|
opp-201500000 { |
|
opp-hz = /bits/ 64 <201500000>; |
|
required-opps = <&rpmhpd_opp_svs_l1>; |
|
}; |
|
}; |
|
}; |
|
|
|
qspi_opp_table: qspi-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-19200000 { |
|
opp-hz = /bits/ 64 <19200000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-100000000 { |
|
opp-hz = /bits/ 64 <100000000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-150000000 { |
|
opp-hz = /bits/ 64 <150000000>; |
|
required-opps = <&rpmhpd_opp_svs>; |
|
}; |
|
|
|
opp-300000000 { |
|
opp-hz = /bits/ 64 <300000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
}; |
|
}; |
|
|
|
qspi: spi@88df000 { |
|
compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; |
|
reg = <0 0x088df000 0 0x600>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, |
|
<&gcc GCC_QSPI_CORE_CLK>; |
|
clock-names = "iface", "core"; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
operating-points-v2 = <&qspi_opp_table>; |
|
status = "disabled"; |
|
}; |
|
|
|
slim: slim@171c0000 { |
|
compatible = "qcom,slim-ngd-v2.1.0"; |
|
reg = <0 0x171c0000 0 0x2c000>; |
|
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
qcom,apps-ch-pipes = <0x780000>; |
|
qcom,ea-pc = <0x270>; |
|
status = "okay"; |
|
dmas = <&slimbam 3>, <&slimbam 4>, |
|
<&slimbam 5>, <&slimbam 6>; |
|
dma-names = "rx", "tx", "tx2", "rx2"; |
|
|
|
iommus = <&apps_smmu 0x1806 0x0>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
ngd@1 { |
|
reg = <1>; |
|
#address-cells = <2>; |
|
#size-cells = <0>; |
|
|
|
wcd9340_ifd: ifd@0{ |
|
compatible = "slim217,250"; |
|
reg = <0 0>; |
|
}; |
|
|
|
wcd9340: codec@1{ |
|
compatible = "slim217,250"; |
|
reg = <1 0>; |
|
slim-ifc-dev = <&wcd9340_ifd>; |
|
|
|
#sound-dai-cells = <1>; |
|
|
|
interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-controller; |
|
#interrupt-cells = <1>; |
|
|
|
#clock-cells = <0>; |
|
clock-frequency = <9600000>; |
|
clock-output-names = "mclk"; |
|
qcom,micbias1-millivolt = <1800>; |
|
qcom,micbias2-millivolt = <1800>; |
|
qcom,micbias3-millivolt = <1800>; |
|
qcom,micbias4-millivolt = <1800>; |
|
|
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
|
|
wcdgpio: gpio-controller@42 { |
|
compatible = "qcom,wcd9340-gpio"; |
|
gpio-controller; |
|
#gpio-cells = <2>; |
|
reg = <0x42 0x2>; |
|
}; |
|
|
|
swm: swm@c85 { |
|
compatible = "qcom,soundwire-v1.3.0"; |
|
reg = <0xc85 0x40>; |
|
interrupts-extended = <&wcd9340 20>; |
|
|
|
qcom,dout-ports = <6>; |
|
qcom,din-ports = <2>; |
|
qcom,ports-sinterval-low =/bits/ 8 <0x07 0x1F 0x3F 0x7 0x1F 0x3F 0x0F 0x0F>; |
|
qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0C 0x6 0x12 0x0D 0x07 0x0A >; |
|
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x1F 0x00 0x00 0x1F 0x00 0x00>; |
|
|
|
#sound-dai-cells = <1>; |
|
clocks = <&wcd9340>; |
|
clock-names = "iface"; |
|
#address-cells = <2>; |
|
#size-cells = <0>; |
|
|
|
|
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
sound: sound { |
|
}; |
|
|
|
usb_1_hsphy: phy@88e2000 { |
|
compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; |
|
reg = <0 0x088e2000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "cfg_ahb", "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
|
|
|
nvmem-cells = <&qusb2p_hstx_trim>; |
|
}; |
|
|
|
usb_2_hsphy: phy@88e3000 { |
|
compatible = "qcom,sdm845-qusb2-phy", "qcom,qusb2-v2-phy"; |
|
reg = <0 0x088e3000 0 0x400>; |
|
status = "disabled"; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "cfg_ahb", "ref"; |
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
|
|
|
nvmem-cells = <&qusb2s_hstx_trim>; |
|
}; |
|
|
|
usb_1_qmpphy: phy@88e9000 { |
|
compatible = "qcom,sdm845-qmp-usb3-phy"; |
|
reg = <0 0x088e9000 0 0x18c>, |
|
<0 0x088e8000 0 0x10>; |
|
reg-names = "reg-base", "dp_com"; |
|
status = "disabled"; |
|
#clock-cells = <1>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
|
<&gcc GCC_USB3_PRIM_CLKREF_CLK>, |
|
<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
|
clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
|
|
|
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
|
<&gcc GCC_USB3_PHY_PRIM_BCR>; |
|
reset-names = "phy", "common"; |
|
|
|
usb_1_ssphy: lanes@88e9200 { |
|
reg = <0 0x088e9200 0 0x128>, |
|
<0 0x088e9400 0 0x200>, |
|
<0 0x088e9c00 0 0x218>, |
|
<0 0x088e9600 0 0x128>, |
|
<0 0x088e9800 0 0x200>, |
|
<0 0x088e9a00 0 0x100>; |
|
#phy-cells = <0>; |
|
clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_phy_pipe_clk_src"; |
|
}; |
|
}; |
|
|
|
usb_2_qmpphy: phy@88eb000 { |
|
compatible = "qcom,sdm845-qmp-usb3-uni-phy"; |
|
reg = <0 0x088eb000 0 0x18c>; |
|
status = "disabled"; |
|
#clock-cells = <1>; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
|
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
|
<&gcc GCC_USB3_SEC_CLKREF_CLK>, |
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
|
clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
|
|
|
resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
|
<&gcc GCC_USB3_PHY_SEC_BCR>; |
|
reset-names = "phy", "common"; |
|
|
|
usb_2_ssphy: lane@88eb200 { |
|
reg = <0 0x088eb200 0 0x128>, |
|
<0 0x088eb400 0 0x1fc>, |
|
<0 0x088eb800 0 0x218>, |
|
<0 0x088eb600 0 0x70>; |
|
#phy-cells = <0>; |
|
clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
|
clock-names = "pipe0"; |
|
clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
|
}; |
|
}; |
|
|
|
usb_1: usb@a6f8800 { |
|
compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; |
|
reg = <0 0x0a6f8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_SLEEP_CLK>; |
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
|
"sleep"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_PRIM_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <150000000>; |
|
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hs_phy_irq", "ss_phy_irq", |
|
"dm_hs_phy_irq", "dp_hs_phy_irq"; |
|
|
|
power-domains = <&gcc USB30_PRIM_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_PRIM_BCR>; |
|
|
|
interconnects = <&aggre2_noc MASTER_USB3_0 0 &mem_noc SLAVE_EBI1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; |
|
interconnect-names = "usb-ddr", "apps-usb"; |
|
|
|
usb_1_dwc3: dwc3@a600000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x0a600000 0 0xcd00>; |
|
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x740 0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_1_hsphy>, <&usb_1_ssphy>; |
|
phy-names = "usb2-phy", "usb3-phy"; |
|
}; |
|
}; |
|
|
|
usb_2: usb@a8f8800 { |
|
compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; |
|
reg = <0 0x0a8f8800 0 0x400>; |
|
status = "disabled"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
dma-ranges; |
|
|
|
clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>, |
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>; |
|
clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
|
"sleep"; |
|
|
|
assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
|
<&gcc GCC_USB30_SEC_MASTER_CLK>; |
|
assigned-clock-rates = <19200000>, <150000000>; |
|
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hs_phy_irq", "ss_phy_irq", |
|
"dm_hs_phy_irq", "dp_hs_phy_irq"; |
|
|
|
power-domains = <&gcc USB30_SEC_GDSC>; |
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>; |
|
|
|
interconnects = <&aggre2_noc MASTER_USB3_1 0 &mem_noc SLAVE_EBI1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; |
|
interconnect-names = "usb-ddr", "apps-usb"; |
|
|
|
usb_2_dwc3: dwc3@a800000 { |
|
compatible = "snps,dwc3"; |
|
reg = <0 0x0a800000 0 0xcd00>; |
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x760 0>; |
|
snps,dis_u2_susphy_quirk; |
|
snps,dis_enblslpm_quirk; |
|
phys = <&usb_2_hsphy>, <&usb_2_ssphy>; |
|
phy-names = "usb2-phy", "usb3-phy"; |
|
}; |
|
}; |
|
|
|
venus: video-codec@aa00000 { |
|
compatible = "qcom,sdm845-venus-v2"; |
|
reg = <0 0x0aa00000 0 0xff000>; |
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
|
power-domains = <&videocc VENUS_GDSC>, |
|
<&videocc VCODEC0_GDSC>, |
|
<&videocc VCODEC1_GDSC>, |
|
<&rpmhpd SDM845_CX>; |
|
power-domain-names = "venus", "vcodec0", "vcodec1", "cx"; |
|
operating-points-v2 = <&venus_opp_table>; |
|
clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, |
|
<&videocc VIDEO_CC_VENUS_AHB_CLK>, |
|
<&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, |
|
<&videocc VIDEO_CC_VCODEC0_CORE_CLK>, |
|
<&videocc VIDEO_CC_VCODEC0_AXI_CLK>, |
|
<&videocc VIDEO_CC_VCODEC1_CORE_CLK>, |
|
<&videocc VIDEO_CC_VCODEC1_AXI_CLK>; |
|
clock-names = "core", "iface", "bus", |
|
"vcodec0_core", "vcodec0_bus", |
|
"vcodec1_core", "vcodec1_bus"; |
|
iommus = <&apps_smmu 0x10a0 0x8>, |
|
<&apps_smmu 0x10b0 0x0>; |
|
memory-region = <&venus_mem>; |
|
interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mem_noc SLAVE_EBI1 0>, |
|
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>; |
|
interconnect-names = "video-mem", "cpu-cfg"; |
|
|
|
video-core0 { |
|
compatible = "venus-decoder"; |
|
}; |
|
|
|
video-core1 { |
|
compatible = "venus-encoder"; |
|
}; |
|
|
|
venus_opp_table: venus-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-100000000 { |
|
opp-hz = /bits/ 64 <100000000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-200000000 { |
|
opp-hz = /bits/ 64 <200000000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-320000000 { |
|
opp-hz = /bits/ 64 <320000000>; |
|
required-opps = <&rpmhpd_opp_svs>; |
|
}; |
|
|
|
opp-380000000 { |
|
opp-hz = /bits/ 64 <380000000>; |
|
required-opps = <&rpmhpd_opp_svs_l1>; |
|
}; |
|
|
|
opp-444000000 { |
|
opp-hz = /bits/ 64 <444000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
}; |
|
|
|
opp-533000097 { |
|
opp-hz = /bits/ 64 <533000097>; |
|
required-opps = <&rpmhpd_opp_turbo>; |
|
}; |
|
}; |
|
}; |
|
|
|
videocc: clock-controller@ab00000 { |
|
compatible = "qcom,sdm845-videocc"; |
|
reg = <0 0x0ab00000 0 0x10000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "bi_tcxo"; |
|
#clock-cells = <1>; |
|
#power-domain-cells = <1>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
cci: cci@ac4a000 { |
|
compatible = "qcom,sdm845-cci"; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
reg = <0 0x0ac4a000 0 0x4000>; |
|
interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; |
|
power-domains = <&clock_camcc TITAN_TOP_GDSC>; |
|
|
|
clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
|
<&clock_camcc CAM_CC_SOC_AHB_CLK>, |
|
<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, |
|
<&clock_camcc CAM_CC_CPAS_AHB_CLK>, |
|
<&clock_camcc CAM_CC_CCI_CLK>, |
|
<&clock_camcc CAM_CC_CCI_CLK_SRC>; |
|
clock-names = "camnoc_axi", |
|
"soc_ahb", |
|
"slow_ahb_src", |
|
"cpas_ahb", |
|
"cci", |
|
"cci_src"; |
|
|
|
assigned-clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, |
|
<&clock_camcc CAM_CC_CCI_CLK>; |
|
assigned-clock-rates = <80000000>, <37500000>; |
|
|
|
pinctrl-names = "default", "sleep"; |
|
pinctrl-0 = <&cci0_default &cci1_default>; |
|
pinctrl-1 = <&cci0_sleep &cci1_sleep>; |
|
|
|
status = "disabled"; |
|
|
|
cci_i2c0: i2c-bus@0 { |
|
reg = <0>; |
|
clock-frequency = <1000000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
|
|
cci_i2c1: i2c-bus@1 { |
|
reg = <1>; |
|
clock-frequency = <1000000>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
}; |
|
}; |
|
|
|
clock_camcc: clock-controller@ad00000 { |
|
compatible = "qcom,sdm845-camcc"; |
|
reg = <0 0x0ad00000 0 0x10000>; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
dsi_opp_table: dsi-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-19200000 { |
|
opp-hz = /bits/ 64 <19200000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-180000000 { |
|
opp-hz = /bits/ 64 <180000000>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-275000000 { |
|
opp-hz = /bits/ 64 <275000000>; |
|
required-opps = <&rpmhpd_opp_svs>; |
|
}; |
|
|
|
opp-328580000 { |
|
opp-hz = /bits/ 64 <328580000>; |
|
required-opps = <&rpmhpd_opp_svs_l1>; |
|
}; |
|
|
|
opp-358000000 { |
|
opp-hz = /bits/ 64 <358000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
}; |
|
}; |
|
|
|
mdss: mdss@ae00000 { |
|
compatible = "qcom,sdm845-mdss"; |
|
reg = <0 0x0ae00000 0 0x1000>; |
|
reg-names = "mdss"; |
|
|
|
power-domains = <&dispcc MDSS_GDSC>; |
|
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>, |
|
<&gcc GCC_DISP_AXI_CLK>, |
|
<&dispcc DISP_CC_MDSS_MDP_CLK>; |
|
clock-names = "iface", "bus", "core"; |
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; |
|
assigned-clock-rates = <300000000>; |
|
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-controller; |
|
#interrupt-cells = <1>; |
|
|
|
interconnects = <&mmss_noc MASTER_MDP0 0 &mem_noc SLAVE_EBI1 0>, |
|
<&mmss_noc MASTER_MDP1 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "mdp0-mem", "mdp1-mem"; |
|
|
|
iommus = <&apps_smmu 0x880 0x8>, |
|
<&apps_smmu 0xc80 0x8>; |
|
|
|
status = "disabled"; |
|
|
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
|
|
mdss_mdp: mdp@ae01000 { |
|
compatible = "qcom,sdm845-dpu"; |
|
reg = <0 0x0ae01000 0 0x8f000>, |
|
<0 0x0aeb0000 0 0x2008>; |
|
reg-names = "mdp", "vbif"; |
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
|
<&dispcc DISP_CC_MDSS_AXI_CLK>, |
|
<&dispcc DISP_CC_MDSS_MDP_CLK>, |
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
|
clock-names = "iface", "bus", "core", "vsync"; |
|
|
|
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, |
|
<&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
|
assigned-clock-rates = <300000000>, |
|
<19200000>; |
|
operating-points-v2 = <&mdp_opp_table>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
|
|
interrupt-parent = <&mdss>; |
|
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
status = "disabled"; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
dpu_intf1_out: endpoint { |
|
remote-endpoint = <&dsi0_in>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
dpu_intf2_out: endpoint { |
|
remote-endpoint = <&dsi1_in>; |
|
}; |
|
}; |
|
}; |
|
|
|
mdp_opp_table: mdp-opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-19200000 { |
|
opp-hz = /bits/ 64 <19200000>; |
|
required-opps = <&rpmhpd_opp_min_svs>; |
|
}; |
|
|
|
opp-171428571 { |
|
opp-hz = /bits/ 64 <171428571>; |
|
required-opps = <&rpmhpd_opp_low_svs>; |
|
}; |
|
|
|
opp-344000000 { |
|
opp-hz = /bits/ 64 <344000000>; |
|
required-opps = <&rpmhpd_opp_svs_l1>; |
|
}; |
|
|
|
opp-430000000 { |
|
opp-hz = /bits/ 64 <430000000>; |
|
required-opps = <&rpmhpd_opp_nom>; |
|
}; |
|
}; |
|
}; |
|
|
|
dsi0: dsi@ae94000 { |
|
compatible = "qcom,mdss-dsi-ctrl"; |
|
reg = <0 0x0ae94000 0 0x400>; |
|
reg-names = "dsi_ctrl"; |
|
|
|
interrupt-parent = <&mdss>; |
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, |
|
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
|
<&dispcc DISP_CC_MDSS_PCLK0_CLK>, |
|
<&dispcc DISP_CC_MDSS_ESC0_CLK>, |
|
<&dispcc DISP_CC_MDSS_AHB_CLK>, |
|
<&dispcc DISP_CC_MDSS_AXI_CLK>; |
|
clock-names = "byte", |
|
"byte_intf", |
|
"pixel", |
|
"core", |
|
"iface", |
|
"bus"; |
|
operating-points-v2 = <&dsi_opp_table>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
|
|
phys = <&dsi0_phy>; |
|
phy-names = "dsi"; |
|
|
|
status = "disabled"; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
dsi0_in: endpoint { |
|
remote-endpoint = <&dpu_intf1_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
dsi0_out: endpoint { |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
dsi0_phy: dsi-phy@ae94400 { |
|
compatible = "qcom,dsi-phy-10nm"; |
|
reg = <0 0x0ae94400 0 0x200>, |
|
<0 0x0ae94600 0 0x280>, |
|
<0 0x0ae94a00 0 0x1e0>; |
|
reg-names = "dsi_phy", |
|
"dsi_phy_lane", |
|
"dsi_pll"; |
|
|
|
#clock-cells = <1>; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "iface", "ref"; |
|
|
|
status = "disabled"; |
|
}; |
|
|
|
dsi1: dsi@ae96000 { |
|
compatible = "qcom,mdss-dsi-ctrl"; |
|
reg = <0 0x0ae96000 0 0x400>; |
|
reg-names = "dsi_ctrl"; |
|
|
|
interrupt-parent = <&mdss>; |
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, |
|
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, |
|
<&dispcc DISP_CC_MDSS_PCLK1_CLK>, |
|
<&dispcc DISP_CC_MDSS_ESC1_CLK>, |
|
<&dispcc DISP_CC_MDSS_AHB_CLK>, |
|
<&dispcc DISP_CC_MDSS_AXI_CLK>; |
|
clock-names = "byte", |
|
"byte_intf", |
|
"pixel", |
|
"core", |
|
"iface", |
|
"bus"; |
|
operating-points-v2 = <&dsi_opp_table>; |
|
power-domains = <&rpmhpd SDM845_CX>; |
|
|
|
phys = <&dsi1_phy>; |
|
phy-names = "dsi"; |
|
|
|
status = "disabled"; |
|
|
|
ports { |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
|
|
port@0 { |
|
reg = <0>; |
|
dsi1_in: endpoint { |
|
remote-endpoint = <&dpu_intf2_out>; |
|
}; |
|
}; |
|
|
|
port@1 { |
|
reg = <1>; |
|
dsi1_out: endpoint { |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
dsi1_phy: dsi-phy@ae96400 { |
|
compatible = "qcom,dsi-phy-10nm"; |
|
reg = <0 0x0ae96400 0 0x200>, |
|
<0 0x0ae96600 0 0x280>, |
|
<0 0x0ae96a00 0 0x10e>; |
|
reg-names = "dsi_phy", |
|
"dsi_phy_lane", |
|
"dsi_pll"; |
|
|
|
#clock-cells = <1>; |
|
#phy-cells = <0>; |
|
|
|
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
|
<&rpmhcc RPMH_CXO_CLK>; |
|
clock-names = "iface", "ref"; |
|
|
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
gpu: gpu@5000000 { |
|
compatible = "qcom,adreno-630.2", "qcom,adreno"; |
|
#stream-id-cells = <16>; |
|
|
|
reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; |
|
reg-names = "kgsl_3d0_reg_memory", "cx_mem"; |
|
|
|
/* |
|
* Look ma, no clocks! The GPU clocks and power are |
|
* controlled entirely by the GMU |
|
*/ |
|
|
|
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
iommus = <&adreno_smmu 0>; |
|
|
|
operating-points-v2 = <&gpu_opp_table>; |
|
|
|
qcom,gmu = <&gmu>; |
|
|
|
interconnects = <&mem_noc MASTER_GFX3D 0 &mem_noc SLAVE_EBI1 0>; |
|
interconnect-names = "gfx-mem"; |
|
|
|
gpu_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-710000000 { |
|
opp-hz = /bits/ 64 <710000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
|
opp-peak-kBps = <7216000>; |
|
}; |
|
|
|
opp-675000000 { |
|
opp-hz = /bits/ 64 <675000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
|
opp-peak-kBps = <7216000>; |
|
}; |
|
|
|
opp-596000000 { |
|
opp-hz = /bits/ 64 <596000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
|
opp-peak-kBps = <6220000>; |
|
}; |
|
|
|
opp-520000000 { |
|
opp-hz = /bits/ 64 <520000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
|
opp-peak-kBps = <6220000>; |
|
}; |
|
|
|
opp-414000000 { |
|
opp-hz = /bits/ 64 <414000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
|
opp-peak-kBps = <4068000>; |
|
}; |
|
|
|
opp-342000000 { |
|
opp-hz = /bits/ 64 <342000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
opp-peak-kBps = <2724000>; |
|
}; |
|
|
|
opp-257000000 { |
|
opp-hz = /bits/ 64 <257000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
|
opp-peak-kBps = <1648000>; |
|
}; |
|
}; |
|
}; |
|
|
|
adreno_smmu: iommu@5040000 { |
|
compatible = "qcom,sdm845-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; |
|
reg = <0 0x5040000 0 0x10000>; |
|
#iommu-cells = <1>; |
|
#global-interrupts = <2>; |
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, |
|
<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; |
|
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
|
<&gcc GCC_GPU_CFG_AHB_CLK>; |
|
clock-names = "bus", "iface"; |
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>; |
|
}; |
|
|
|
gmu: gmu@506a000 { |
|
compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; |
|
|
|
reg = <0 0x506a000 0 0x30000>, |
|
<0 0xb280000 0 0x10000>, |
|
<0 0xb480000 0 0x10000>; |
|
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; |
|
|
|
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "hfi", "gmu"; |
|
|
|
clocks = <&gpucc GPU_CC_CX_GMU_CLK>, |
|
<&gpucc GPU_CC_CXO_CLK>, |
|
<&gcc GCC_DDRSS_GPU_AXI_CLK>, |
|
<&gcc GCC_GPU_MEMNOC_GFX_CLK>; |
|
clock-names = "gmu", "cxo", "axi", "memnoc"; |
|
|
|
power-domains = <&gpucc GPU_CX_GDSC>, |
|
<&gpucc GPU_GX_GDSC>; |
|
power-domain-names = "cx", "gx"; |
|
|
|
iommus = <&adreno_smmu 5>; |
|
|
|
operating-points-v2 = <&gmu_opp_table>; |
|
|
|
gmu_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
opp-400000000 { |
|
opp-hz = /bits/ 64 <400000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
}; |
|
|
|
opp-200000000 { |
|
opp-hz = /bits/ 64 <200000000>; |
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
|
}; |
|
}; |
|
}; |
|
|
|
dispcc: clock-controller@af00000 { |
|
compatible = "qcom,sdm845-dispcc"; |
|
reg = <0 0x0af00000 0 0x10000>; |
|
clocks = <&rpmhcc RPMH_CXO_CLK>, |
|
<&gcc GCC_DISP_GPLL0_CLK_SRC>, |
|
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, |
|
<&dsi0_phy 0>, |
|
<&dsi0_phy 1>, |
|
<&dsi1_phy 0>, |
|
<&dsi1_phy 1>, |
|
<0>, |
|
<0>; |
|
clock-names = "bi_tcxo", |
|
"gcc_disp_gpll0_clk_src", |
|
"gcc_disp_gpll0_div_clk_src", |
|
"dsi0_phy_pll_out_byteclk", |
|
"dsi0_phy_pll_out_dsiclk", |
|
"dsi1_phy_pll_out_byteclk", |
|
"dsi1_phy_pll_out_dsiclk", |
|
"dp_link_clk_divsel_ten", |
|
"dp_vco_divided_clk_src_mux"; |
|
#clock-cells = <1>; |
|
#reset-cells = <1>; |
|
#power-domain-cells = <1>; |
|
}; |
|
|
|
pdc_intc: interrupt-controller@b220000 { |
|
compatible = "qcom,sdm845-pdc", "qcom,pdc"; |
|
reg = <0 0x0b220000 0 0x30000>; |
|
qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; |
|
#interrupt-cells = <2>; |
|
interrupt-parent = <&intc>; |
|
interrupt-controller; |
|
}; |
|
|
|
pdc_reset: reset-controller@b2e0000 { |
|
compatible = "qcom,sdm845-pdc-global"; |
|
reg = <0 0x0b2e0000 0 0x20000>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
tsens0: thermal-sensor@c263000 { |
|
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; |
|
reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
|
<0 0x0c222000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <13>; |
|
interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow", "critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
tsens1: thermal-sensor@c265000 { |
|
compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; |
|
reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
|
<0 0x0c223000 0 0x1ff>; /* SROT */ |
|
#qcom,sensors = <8>; |
|
interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; |
|
interrupt-names = "uplow", "critical"; |
|
#thermal-sensor-cells = <1>; |
|
}; |
|
|
|
aoss_reset: reset-controller@c2a0000 { |
|
compatible = "qcom,sdm845-aoss-cc"; |
|
reg = <0 0x0c2a0000 0 0x31000>; |
|
#reset-cells = <1>; |
|
}; |
|
|
|
aoss_qmp: qmp@c300000 { |
|
compatible = "qcom,sdm845-aoss-qmp"; |
|
reg = <0 0x0c300000 0 0x100000>; |
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; |
|
mboxes = <&apss_shared 0>; |
|
|
|
#clock-cells = <0>; |
|
#power-domain-cells = <1>; |
|
|
|
cx_cdev: cx { |
|
#cooling-cells = <2>; |
|
}; |
|
|
|
ebi_cdev: ebi { |
|
#cooling-cells = <2>; |
|
}; |
|
}; |
|
|
|
spmi_bus: spmi@c440000 { |
|
compatible = "qcom,spmi-pmic-arb"; |
|
reg = <0 0x0c440000 0 0x1100>, |
|
<0 0x0c600000 0 0x2000000>, |
|
<0 0x0e600000 0 0x100000>, |
|
<0 0x0e700000 0 0xa0000>, |
|
<0 0x0c40a000 0 0x26000>; |
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
|
interrupt-names = "periph_irq"; |
|
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,ee = <0>; |
|
qcom,channel = <0>; |
|
#address-cells = <2>; |
|
#size-cells = <0>; |
|
interrupt-controller; |
|
#interrupt-cells = <4>; |
|
cell-index = <0>; |
|
}; |
|
|
|
imem@146bf000 { |
|
compatible = "simple-mfd"; |
|
reg = <0 0x146bf000 0 0x1000>; |
|
|
|
#address-cells = <1>; |
|
#size-cells = <1>; |
|
|
|
ranges = <0 0 0x146bf000 0x1000>; |
|
|
|
pil-reloc@94c { |
|
compatible = "qcom,pil-reloc-info"; |
|
reg = <0x94c 0xc8>; |
|
}; |
|
}; |
|
|
|
apps_smmu: iommu@15000000 { |
|
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; |
|
reg = <0 0x15000000 0 0x80000>; |
|
#iommu-cells = <2>; |
|
#global-interrupts = <1>; |
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
lpasscc: clock-controller@17014000 { |
|
compatible = "qcom,sdm845-lpasscc"; |
|
reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; |
|
reg-names = "cc", "qdsp6ss"; |
|
#clock-cells = <1>; |
|
status = "disabled"; |
|
}; |
|
|
|
gladiator_noc: interconnect@17900000 { |
|
compatible = "qcom,sdm845-gladiator-noc"; |
|
reg = <0 0x17900000 0 0xd080>; |
|
#interconnect-cells = <2>; |
|
qcom,bcm-voters = <&apps_bcm_voter>; |
|
}; |
|
|
|
watchdog@17980000 { |
|
compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; |
|
reg = <0 0x17980000 0 0x1000>; |
|
clocks = <&sleep_clk>; |
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
|
}; |
|
|
|
apss_shared: mailbox@17990000 { |
|
compatible = "qcom,sdm845-apss-shared"; |
|
reg = <0 0x17990000 0 0x1000>; |
|
#mbox-cells = <1>; |
|
}; |
|
|
|
apps_rsc: rsc@179c0000 { |
|
label = "apps_rsc"; |
|
compatible = "qcom,rpmh-rsc"; |
|
reg = <0 0x179c0000 0 0x10000>, |
|
<0 0x179d0000 0 0x10000>, |
|
<0 0x179e0000 0 0x10000>; |
|
reg-names = "drv-0", "drv-1", "drv-2"; |
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
|
qcom,tcs-offset = <0xd00>; |
|
qcom,drv-id = <2>; |
|
qcom,tcs-config = <ACTIVE_TCS 2>, |
|
<SLEEP_TCS 3>, |
|
<WAKE_TCS 3>, |
|
<CONTROL_TCS 1>; |
|
|
|
apps_bcm_voter: bcm-voter { |
|
compatible = "qcom,bcm-voter"; |
|
}; |
|
|
|
rpmhcc: clock-controller { |
|
compatible = "qcom,sdm845-rpmh-clk"; |
|
#clock-cells = <1>; |
|
clock-names = "xo"; |
|
clocks = <&xo_board>; |
|
}; |
|
|
|
rpmhpd: power-controller { |
|
compatible = "qcom,sdm845-rpmhpd"; |
|
#power-domain-cells = <1>; |
|
operating-points-v2 = <&rpmhpd_opp_table>; |
|
|
|
rpmhpd_opp_table: opp-table { |
|
compatible = "operating-points-v2"; |
|
|
|
rpmhpd_opp_ret: opp1 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; |
|
}; |
|
|
|
rpmhpd_opp_min_svs: opp2 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_low_svs: opp3 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs: opp4 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
|
}; |
|
|
|
rpmhpd_opp_svs_l1: opp5 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
|
}; |
|
|
|
rpmhpd_opp_nom: opp6 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
|
}; |
|
|
|
rpmhpd_opp_nom_l1: opp7 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
|
}; |
|
|
|
rpmhpd_opp_nom_l2: opp8 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; |
|
}; |
|
|
|
rpmhpd_opp_turbo: opp9 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
|
}; |
|
|
|
rpmhpd_opp_turbo_l1: opp10 { |
|
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
|
}; |
|
}; |
|
}; |
|
}; |
|
|
|
intc: interrupt-controller@17a00000 { |
|
compatible = "arm,gic-v3"; |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
#interrupt-cells = <3>; |
|
interrupt-controller; |
|
reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
|
<0 0x17a60000 0 0x100000>; /* GICR * 8 */ |
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
|
|
msi-controller@17a40000 { |
|
compatible = "arm,gic-v3-its"; |
|
msi-controller; |
|
#msi-cells = <1>; |
|
reg = <0 0x17a40000 0 0x20000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
slimbam: dma-controller@17184000 { |
|
compatible = "qcom,bam-v1.7.0"; |
|
qcom,controlled-remotely; |
|
reg = <0 0x17184000 0 0x2a000>; |
|
num-channels = <31>; |
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
|
#dma-cells = <1>; |
|
qcom,ee = <1>; |
|
qcom,num-ees = <2>; |
|
iommus = <&apps_smmu 0x1806 0x0>; |
|
}; |
|
|
|
timer@17c90000 { |
|
#address-cells = <2>; |
|
#size-cells = <2>; |
|
ranges; |
|
compatible = "arm,armv7-timer-mem"; |
|
reg = <0 0x17c90000 0 0x1000>; |
|
|
|
frame@17ca0000 { |
|
frame-number = <0>; |
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17ca0000 0 0x1000>, |
|
<0 0x17cb0000 0 0x1000>; |
|
}; |
|
|
|
frame@17cc0000 { |
|
frame-number = <1>; |
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17cc0000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17cd0000 { |
|
frame-number = <2>; |
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17cd0000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17ce0000 { |
|
frame-number = <3>; |
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17ce0000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17cf0000 { |
|
frame-number = <4>; |
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17cf0000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17d00000 { |
|
frame-number = <5>; |
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17d00000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
|
|
frame@17d10000 { |
|
frame-number = <6>; |
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
|
reg = <0 0x17d10000 0 0x1000>; |
|
status = "disabled"; |
|
}; |
|
}; |
|
|
|
osm_l3: interconnect@17d41000 { |
|
compatible = "qcom,sdm845-osm-l3"; |
|
reg = <0 0x17d41000 0 0x1400>; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
|
clock-names = "xo", "alternate"; |
|
|
|
#interconnect-cells = <1>; |
|
}; |
|
|
|
cpufreq_hw: cpufreq@17d43000 { |
|
compatible = "qcom,cpufreq-hw"; |
|
reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; |
|
reg-names = "freq-domain0", "freq-domain1"; |
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
|
clock-names = "xo", "alternate"; |
|
|
|
#freq-domain-cells = <1>; |
|
}; |
|
|
|
wifi: wifi@18800000 { |
|
compatible = "qcom,wcn3990-wifi"; |
|
status = "disabled"; |
|
reg = <0 0x18800000 0 0x800000>; |
|
reg-names = "membase"; |
|
memory-region = <&wlan_msa_mem>; |
|
clock-names = "cxo_ref_clk_pin"; |
|
clocks = <&rpmhcc RPMH_RF_CLK2>; |
|
interrupts = |
|
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
|
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; |
|
iommus = <&apps_smmu 0x0040 0x1>; |
|
}; |
|
}; |
|
|
|
thermal-zones { |
|
cpu0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 1>; |
|
|
|
trips { |
|
cpu0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu0_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu0_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu0_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 2>; |
|
|
|
trips { |
|
cpu1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu1_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu1_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu1_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu2-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 3>; |
|
|
|
trips { |
|
cpu2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu2_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu2_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu2_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu3-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 4>; |
|
|
|
trips { |
|
cpu3_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu3_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu3_alert0>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu3_alert1>; |
|
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu4-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 7>; |
|
|
|
trips { |
|
cpu4_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu4_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu4_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu4_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu5-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 8>; |
|
|
|
trips { |
|
cpu5_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu5_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu5_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu5_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu6-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 9>; |
|
|
|
trips { |
|
cpu6_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu6_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu6_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu6_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
cpu7-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 10>; |
|
|
|
trips { |
|
cpu7_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_alert1: trip-point1 { |
|
temperature = <95000>; |
|
hysteresis = <2000>; |
|
type = "passive"; |
|
}; |
|
|
|
cpu7_crit: cpu_crit { |
|
temperature = <110000>; |
|
hysteresis = <1000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
|
|
cooling-maps { |
|
map0 { |
|
trip = <&cpu7_alert0>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
map1 { |
|
trip = <&cpu7_alert1>; |
|
cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
|
<&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 0>; |
|
|
|
trips { |
|
aoss0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
cluster0-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 5>; |
|
|
|
trips { |
|
cluster0_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cluster0_crit: cluster0_crit { |
|
temperature = <110000>; |
|
hysteresis = <2000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
cluster1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 6>; |
|
|
|
trips { |
|
cluster1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
cluster1_crit: cluster1_crit { |
|
temperature = <110000>; |
|
hysteresis = <2000>; |
|
type = "critical"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu-thermal-top { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 11>; |
|
|
|
trips { |
|
gpu1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
gpu-thermal-bottom { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens0 12>; |
|
|
|
trips { |
|
gpu2_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
aoss1-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 0>; |
|
|
|
trips { |
|
aoss1_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
q6-modem-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 1>; |
|
|
|
trips { |
|
q6_modem_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
mem-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 2>; |
|
|
|
trips { |
|
mem_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
wlan-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 3>; |
|
|
|
trips { |
|
wlan_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
q6-hvx-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 4>; |
|
|
|
trips { |
|
q6_hvx_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
camera-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 5>; |
|
|
|
trips { |
|
camera_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
video-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 6>; |
|
|
|
trips { |
|
video_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
|
|
modem-thermal { |
|
polling-delay-passive = <250>; |
|
polling-delay = <1000>; |
|
|
|
thermal-sensors = <&tsens1 7>; |
|
|
|
trips { |
|
modem_alert0: trip-point0 { |
|
temperature = <90000>; |
|
hysteresis = <2000>; |
|
type = "hot"; |
|
}; |
|
}; |
|
}; |
|
}; |
|
};
|
|
|