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269 lines
7.4 KiB
269 lines
7.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* ARM Ltd. Fast Models |
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* |
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* Architecture Envelope Model (AEM) ARMv8-A |
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* ARMAEMv8AMPCT |
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* |
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* FVP Base RevC |
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*/ |
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/dts-v1/; |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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/memreserve/ 0x80000000 0x00010000; |
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#include "rtsm_ve-motherboard.dtsi" |
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#include "rtsm_ve-motherboard-rs2.dtsi" |
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/ { |
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model = "FVP Base RevC"; |
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compatible = "arm,fvp-base-revc", "arm,vexpress"; |
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interrupt-parent = <&gic>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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chosen { }; |
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aliases { |
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serial0 = &v2m_serial0; |
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serial1 = &v2m_serial1; |
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serial2 = &v2m_serial2; |
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serial3 = &v2m_serial3; |
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}; |
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psci { |
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compatible = "arm,psci-0.2"; |
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method = "smc"; |
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}; |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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cpu0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x000>; |
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enable-method = "psci"; |
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}; |
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cpu1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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}; |
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cpu2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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}; |
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cpu3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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}; |
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cpu4: cpu@10000 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x10000>; |
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enable-method = "psci"; |
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}; |
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cpu5: cpu@10100 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x10100>; |
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enable-method = "psci"; |
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}; |
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cpu6: cpu@10200 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x10200>; |
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enable-method = "psci"; |
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}; |
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cpu7: cpu@10300 { |
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device_type = "cpu"; |
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compatible = "arm,armv8"; |
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reg = <0x0 0x10300>; |
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enable-method = "psci"; |
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}; |
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}; |
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memory@80000000 { |
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device_type = "memory"; |
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reg = <0x00000000 0x80000000 0 0x80000000>, |
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<0x00000008 0x80000000 0 0x80000000>; |
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}; |
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reserved-memory { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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/* Chipselect 2,00000000 is physically at 0x18000000 */ |
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vram: vram@18000000 { |
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/* 8 MB of designated video RAM */ |
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compatible = "shared-dma-pool"; |
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reg = <0x00000000 0x18000000 0 0x00800000>; |
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no-map; |
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}; |
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}; |
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gic: interrupt-controller@2f000000 { |
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compatible = "arm,gic-v3"; |
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#interrupt-cells = <3>; |
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#address-cells = <2>; |
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#size-cells = <2>; |
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ranges; |
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interrupt-controller; |
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reg = <0x0 0x2f000000 0 0x10000>, // GICD |
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<0x0 0x2f100000 0 0x200000>, // GICR |
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<0x0 0x2c000000 0 0x2000>, // GICC |
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<0x0 0x2c010000 0 0x2000>, // GICH |
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<0x0 0x2c02f000 0 0x2000>; // GICV |
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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its: msi-controller@2f020000 { |
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#msi-cells = <1>; |
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compatible = "arm,gic-v3-its"; |
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reg = <0x0 0x2f020000 0x0 0x20000>; // GITS |
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msi-controller; |
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}; |
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}; |
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timer { |
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compatible = "arm,armv8-timer"; |
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
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}; |
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pmu { |
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compatible = "arm,armv8-pmuv3"; |
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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spe-pmu { |
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compatible = "arm,statistical-profiling-extension-v1"; |
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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pci: pci@40000000 { |
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#address-cells = <0x3>; |
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#size-cells = <0x2>; |
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#interrupt-cells = <0x1>; |
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compatible = "pci-host-ecam-generic"; |
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device_type = "pci"; |
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bus-range = <0x0 0x1>; |
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reg = <0x0 0x40000000 0x0 0x10000000>; |
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ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>; |
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interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 2 &gic 0 0 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 3 &gic 0 0 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 0 4 &gic 0 0 GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; |
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interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
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msi-map = <0x0 &its 0x0 0x10000>; |
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iommu-map = <0x0 &smmu 0x0 0x10000>; |
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dma-coherent; |
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}; |
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smmu: iommu@2b400000 { |
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compatible = "arm,smmu-v3"; |
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reg = <0x0 0x2b400000 0x0 0x100000>; |
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interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, |
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<GIC_SPI 77 IRQ_TYPE_EDGE_RISING>; |
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interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; |
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dma-coherent; |
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#iommu-cells = <1>; |
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msi-parent = <&its 0x10000>; |
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}; |
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panel { |
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compatible = "arm,rtsm-display", "panel-dpi"; |
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port { |
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panel_in: endpoint { |
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remote-endpoint = <&clcd_pads>; |
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}; |
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}; |
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panel-timing { |
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clock-frequency = <63500127>; |
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hactive = <1024>; |
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hback-porch = <152>; |
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hfront-porch = <48>; |
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hsync-len = <104>; |
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vactive = <768>; |
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vback-porch = <23>; |
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vfront-porch = <3>; |
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vsync-len = <4>; |
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}; |
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}; |
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bus@8000000 { |
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compatible = "simple-bus"; |
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#address-cells = <2>; |
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#size-cells = <1>; |
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ranges = <0 0 0 0x08000000 0x04000000>, |
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<1 0 0 0x14000000 0x04000000>, |
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<2 0 0 0x18000000 0x04000000>, |
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<3 0 0 0x1c000000 0x04000000>, |
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<4 0 0 0x0c000000 0x04000000>, |
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<5 0 0 0x10000000 0x04000000>; |
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#interrupt-cells = <1>; |
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interrupt-map-mask = <0 0 63>; |
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interrupt-map = <0 0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 1 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 2 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 3 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 4 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 5 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 6 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 7 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 8 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 9 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 10 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 11 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 12 &gic 0 0 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 13 &gic 0 0 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 14 &gic 0 0 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 15 &gic 0 0 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 16 &gic 0 0 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 17 &gic 0 0 GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 18 &gic 0 0 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 19 &gic 0 0 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 20 &gic 0 0 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 21 &gic 0 0 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 22 &gic 0 0 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 23 &gic 0 0 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 24 &gic 0 0 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 25 &gic 0 0 GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 26 &gic 0 0 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 27 &gic 0 0 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 28 &gic 0 0 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 29 &gic 0 0 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 30 &gic 0 0 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 31 &gic 0 0 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 32 &gic 0 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 33 &gic 0 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 34 &gic 0 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 35 &gic 0 0 GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 36 &gic 0 0 GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 37 &gic 0 0 GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 38 &gic 0 0 GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 39 &gic 0 0 GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 40 &gic 0 0 GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 41 &gic 0 0 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 42 &gic 0 0 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 43 &gic 0 0 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
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<0 0 44 &gic 0 0 GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
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}; |
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};
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