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238 lines
5.5 KiB
238 lines
5.5 KiB
/* |
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* arch/arm/plat-orion/time.c |
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* |
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* Marvell Orion SoC timer handling. |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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* |
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* Timer 0 is used as free-running clocksource, while timer 1 is |
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* used as clock_event_device. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/timer.h> |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/sched_clock.h> |
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#include <plat/time.h> |
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#include <asm/delay.h> |
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/* |
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* MBus bridge block registers. |
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*/ |
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#define BRIDGE_CAUSE_OFF 0x0110 |
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#define BRIDGE_MASK_OFF 0x0114 |
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#define BRIDGE_INT_TIMER0 0x0002 |
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#define BRIDGE_INT_TIMER1 0x0004 |
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/* |
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* Timer block registers. |
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*/ |
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#define TIMER_CTRL_OFF 0x0000 |
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#define TIMER0_EN 0x0001 |
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#define TIMER0_RELOAD_EN 0x0002 |
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#define TIMER1_EN 0x0004 |
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#define TIMER1_RELOAD_EN 0x0008 |
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#define TIMER0_RELOAD_OFF 0x0010 |
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#define TIMER0_VAL_OFF 0x0014 |
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#define TIMER1_RELOAD_OFF 0x0018 |
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#define TIMER1_VAL_OFF 0x001c |
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/* |
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* SoC-specific data. |
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*/ |
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static void __iomem *bridge_base; |
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static u32 bridge_timer1_clr_mask; |
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static void __iomem *timer_base; |
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/* |
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* Number of timer ticks per jiffy. |
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*/ |
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static u32 ticks_per_jiffy; |
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/* |
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* Orion's sched_clock implementation. It has a resolution of |
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* at least 7.5ns (133MHz TCLK). |
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*/ |
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static u64 notrace orion_read_sched_clock(void) |
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{ |
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return ~readl(timer_base + TIMER0_VAL_OFF); |
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} |
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/* |
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* Clockevent handling. |
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*/ |
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static int |
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orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev) |
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{ |
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unsigned long flags; |
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u32 u; |
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if (delta == 0) |
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return -ETIME; |
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local_irq_save(flags); |
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/* |
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* Clear and enable clockevent timer interrupt. |
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*/ |
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
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u = readl(bridge_base + BRIDGE_MASK_OFF); |
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u |= BRIDGE_INT_TIMER1; |
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writel(u, bridge_base + BRIDGE_MASK_OFF); |
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/* |
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* Setup new clockevent timer value. |
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*/ |
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writel(delta, timer_base + TIMER1_VAL_OFF); |
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/* |
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* Enable the timer. |
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*/ |
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u = readl(timer_base + TIMER_CTRL_OFF); |
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u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN; |
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writel(u, timer_base + TIMER_CTRL_OFF); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int orion_clkevt_shutdown(struct clock_event_device *evt) |
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{ |
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unsigned long flags; |
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u32 u; |
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local_irq_save(flags); |
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/* Disable timer */ |
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u = readl(timer_base + TIMER_CTRL_OFF); |
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writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); |
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/* Disable timer interrupt */ |
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u = readl(bridge_base + BRIDGE_MASK_OFF); |
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writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); |
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/* ACK pending timer interrupt */ |
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static int orion_clkevt_set_periodic(struct clock_event_device *evt) |
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{ |
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unsigned long flags; |
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u32 u; |
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local_irq_save(flags); |
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/* Setup timer to fire at 1/HZ intervals */ |
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); |
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writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); |
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/* Enable timer interrupt */ |
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u = readl(bridge_base + BRIDGE_MASK_OFF); |
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writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); |
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/* Enable timer */ |
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u = readl(timer_base + TIMER_CTRL_OFF); |
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writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF); |
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local_irq_restore(flags); |
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return 0; |
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} |
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static struct clock_event_device orion_clkevt = { |
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.name = "orion_tick", |
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.features = CLOCK_EVT_FEAT_ONESHOT | |
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CLOCK_EVT_FEAT_PERIODIC, |
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.rating = 300, |
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.set_next_event = orion_clkevt_next_event, |
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.set_state_shutdown = orion_clkevt_shutdown, |
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.set_state_periodic = orion_clkevt_set_periodic, |
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.set_state_oneshot = orion_clkevt_shutdown, |
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.tick_resume = orion_clkevt_shutdown, |
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}; |
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static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) |
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{ |
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/* |
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* ACK timer interrupt and call event handler. |
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*/ |
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writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); |
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orion_clkevt.event_handler(&orion_clkevt); |
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return IRQ_HANDLED; |
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} |
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void __init |
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orion_time_set_base(void __iomem *_timer_base) |
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{ |
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timer_base = _timer_base; |
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} |
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static unsigned long orion_delay_timer_read(void) |
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{ |
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return ~readl(timer_base + TIMER0_VAL_OFF); |
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} |
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static struct delay_timer orion_delay_timer = { |
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.read_current_timer = orion_delay_timer_read, |
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}; |
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void __init |
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orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask, |
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unsigned int irq, unsigned int tclk) |
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{ |
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u32 u; |
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/* |
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* Set SoC-specific data. |
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*/ |
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bridge_base = _bridge_base; |
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bridge_timer1_clr_mask = _bridge_timer1_clr_mask; |
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ticks_per_jiffy = (tclk + HZ/2) / HZ; |
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orion_delay_timer.freq = tclk; |
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register_current_timer_delay(&orion_delay_timer); |
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/* |
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* Set scale and timer for sched_clock. |
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*/ |
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sched_clock_register(orion_read_sched_clock, 32, tclk); |
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/* |
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* Setup free-running clocksource timer (interrupts |
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* disabled). |
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*/ |
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writel(0xffffffff, timer_base + TIMER0_VAL_OFF); |
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writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); |
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u = readl(bridge_base + BRIDGE_MASK_OFF); |
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writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); |
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u = readl(timer_base + TIMER_CTRL_OFF); |
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writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); |
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clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource", |
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tclk, 300, 32, clocksource_mmio_readl_down); |
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/* |
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* Setup clockevent timer (interrupt-driven). |
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*/ |
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if (request_irq(irq, orion_timer_interrupt, IRQF_TIMER, "orion_tick", |
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NULL)) |
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pr_err("Failed to request irq %u (orion_tick)\n", irq); |
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orion_clkevt.cpumask = cpumask_of(0); |
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clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe); |
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}
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