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619 lines
15 KiB
619 lines
15 KiB
/* |
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* arch/arm/plat-orion/gpio.c |
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* |
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* Marvell Orion SoC GPIO handling. |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#define DEBUG |
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|
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/irq.h> |
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#include <linux/irqdomain.h> |
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#include <linux/module.h> |
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#include <linux/spinlock.h> |
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#include <linux/bitops.h> |
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#include <linux/io.h> |
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#include <linux/gpio.h> |
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#include <linux/leds.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_address.h> |
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#include <plat/orion-gpio.h> |
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|
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/* |
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* GPIO unit register offsets. |
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*/ |
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#define GPIO_OUT_OFF 0x0000 |
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#define GPIO_IO_CONF_OFF 0x0004 |
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#define GPIO_BLINK_EN_OFF 0x0008 |
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#define GPIO_IN_POL_OFF 0x000c |
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#define GPIO_DATA_IN_OFF 0x0010 |
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#define GPIO_EDGE_CAUSE_OFF 0x0014 |
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#define GPIO_EDGE_MASK_OFF 0x0018 |
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#define GPIO_LEVEL_MASK_OFF 0x001c |
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|
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struct orion_gpio_chip { |
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struct gpio_chip chip; |
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spinlock_t lock; |
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void __iomem *base; |
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unsigned long valid_input; |
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unsigned long valid_output; |
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int mask_offset; |
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int secondary_irq_base; |
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struct irq_domain *domain; |
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}; |
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|
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static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_OUT_OFF; |
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} |
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|
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static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_IO_CONF_OFF; |
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} |
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|
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static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_BLINK_EN_OFF; |
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} |
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|
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static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_IN_POL_OFF; |
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} |
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|
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static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_DATA_IN_OFF; |
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} |
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|
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static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + GPIO_EDGE_CAUSE_OFF; |
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} |
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|
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static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF; |
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} |
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|
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static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip) |
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{ |
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return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF; |
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} |
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|
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|
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static struct orion_gpio_chip orion_gpio_chips[2]; |
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static int orion_gpio_chip_count; |
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|
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static inline void |
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__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input) |
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{ |
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u32 u; |
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|
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u = readl(GPIO_IO_CONF(ochip)); |
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if (input) |
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u |= 1 << pin; |
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else |
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u &= ~(1 << pin); |
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writel(u, GPIO_IO_CONF(ochip)); |
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} |
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|
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static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high) |
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{ |
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u32 u; |
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|
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u = readl(GPIO_OUT(ochip)); |
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if (high) |
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u |= 1 << pin; |
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else |
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u &= ~(1 << pin); |
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writel(u, GPIO_OUT(ochip)); |
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} |
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|
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static inline void |
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__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink) |
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{ |
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u32 u; |
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|
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u = readl(GPIO_BLINK_EN(ochip)); |
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if (blink) |
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u |= 1 << pin; |
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else |
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u &= ~(1 << pin); |
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writel(u, GPIO_BLINK_EN(ochip)); |
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} |
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|
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static inline int |
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orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode) |
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{ |
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if (pin >= ochip->chip.ngpio) |
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goto err_out; |
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|
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if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input)) |
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goto err_out; |
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|
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if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output)) |
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goto err_out; |
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return 1; |
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|
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err_out: |
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pr_debug("%s: invalid GPIO %d\n", __func__, pin); |
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return false; |
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} |
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|
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/* |
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* GPIO primitives. |
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*/ |
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static int orion_gpio_request(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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|
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if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) || |
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orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) |
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return 0; |
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|
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return -EINVAL; |
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} |
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|
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static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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unsigned long flags; |
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|
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if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK)) |
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return -EINVAL; |
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|
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spin_lock_irqsave(&ochip->lock, flags); |
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__set_direction(ochip, pin, 1); |
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spin_unlock_irqrestore(&ochip->lock, flags); |
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|
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return 0; |
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} |
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|
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static int orion_gpio_get(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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int val; |
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|
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if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) { |
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val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip)); |
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} else { |
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val = readl(GPIO_OUT(ochip)); |
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} |
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|
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return (val >> pin) & 1; |
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} |
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|
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static int |
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orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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unsigned long flags; |
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|
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if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK)) |
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return -EINVAL; |
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|
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spin_lock_irqsave(&ochip->lock, flags); |
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__set_blinking(ochip, pin, 0); |
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__set_level(ochip, pin, value); |
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__set_direction(ochip, pin, 0); |
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spin_unlock_irqrestore(&ochip->lock, flags); |
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|
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return 0; |
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} |
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|
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static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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unsigned long flags; |
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|
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spin_lock_irqsave(&ochip->lock, flags); |
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__set_level(ochip, pin, value); |
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spin_unlock_irqrestore(&ochip->lock, flags); |
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} |
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|
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static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin) |
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{ |
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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|
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return irq_create_mapping(ochip->domain, |
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ochip->secondary_irq_base + pin); |
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} |
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|
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/* |
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* Orion-specific GPIO API extensions. |
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*/ |
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static struct orion_gpio_chip *orion_gpio_chip_find(int pin) |
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{ |
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int i; |
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|
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for (i = 0; i < orion_gpio_chip_count; i++) { |
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struct orion_gpio_chip *ochip = orion_gpio_chips + i; |
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struct gpio_chip *chip = &ochip->chip; |
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|
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if (pin >= chip->base && pin < chip->base + chip->ngpio) |
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return ochip; |
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} |
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|
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return NULL; |
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} |
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|
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void __init orion_gpio_set_unused(unsigned pin) |
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{ |
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
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|
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if (ochip == NULL) |
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return; |
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|
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pin -= ochip->chip.base; |
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|
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/* Configure as output, drive low. */ |
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__set_level(ochip, pin, 0); |
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__set_direction(ochip, pin, 0); |
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} |
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|
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void __init orion_gpio_set_valid(unsigned pin, int mode) |
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{ |
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
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|
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if (ochip == NULL) |
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return; |
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|
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pin -= ochip->chip.base; |
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|
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if (mode == 1) |
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mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; |
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if (mode & GPIO_INPUT_OK) |
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__set_bit(pin, &ochip->valid_input); |
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else |
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__clear_bit(pin, &ochip->valid_input); |
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|
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if (mode & GPIO_OUTPUT_OK) |
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__set_bit(pin, &ochip->valid_output); |
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else |
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__clear_bit(pin, &ochip->valid_output); |
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} |
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|
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void orion_gpio_set_blink(unsigned pin, int blink) |
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{ |
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struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin); |
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unsigned long flags; |
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|
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if (ochip == NULL) |
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return; |
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spin_lock_irqsave(&ochip->lock, flags); |
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__set_level(ochip, pin & 31, 0); |
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__set_blinking(ochip, pin & 31, blink); |
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spin_unlock_irqrestore(&ochip->lock, flags); |
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} |
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EXPORT_SYMBOL(orion_gpio_set_blink); |
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|
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#define ORION_BLINK_HALF_PERIOD 100 /* ms */ |
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|
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int orion_gpio_led_blink_set(struct gpio_desc *desc, int state, |
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unsigned long *delay_on, unsigned long *delay_off) |
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{ |
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unsigned gpio = desc_to_gpio(desc); |
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|
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if (delay_on && delay_off && !*delay_on && !*delay_off) |
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*delay_on = *delay_off = ORION_BLINK_HALF_PERIOD; |
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|
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switch (state) { |
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case GPIO_LED_NO_BLINK_LOW: |
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case GPIO_LED_NO_BLINK_HIGH: |
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orion_gpio_set_blink(gpio, 0); |
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gpio_set_value(gpio, state); |
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break; |
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case GPIO_LED_BLINK: |
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orion_gpio_set_blink(gpio, 1); |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(orion_gpio_led_blink_set); |
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|
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/***************************************************************************** |
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* Orion GPIO IRQ |
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* |
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* GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same |
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* value of the line or the opposite value. |
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* |
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* Level IRQ handlers: DATA_IN is used directly as cause register. |
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* Interrupt are masked by LEVEL_MASK registers. |
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* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. |
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* Interrupt are masked by EDGE_MASK registers. |
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* Both-edge handlers: Similar to regular Edge handlers, but also swaps |
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* the polarity to catch the next line transaction. |
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* This is a race condition that might not perfectly |
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* work on some use cases. |
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* |
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* Every eight GPIO lines are grouped (OR'ed) before going up to main |
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* cause register. |
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* |
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* EDGE cause mask |
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* data-in /--------| |-----| |----\ |
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* -----| |----- ---- to main cause reg |
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* X \----------------| |----/ |
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* polarity LEVEL mask |
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* |
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****************************************************************************/ |
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|
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static int gpio_irq_set_type(struct irq_data *d, u32 type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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struct orion_gpio_chip *ochip = gc->private; |
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int pin; |
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u32 u; |
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|
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pin = d->hwirq - ochip->secondary_irq_base; |
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|
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u = readl(GPIO_IO_CONF(ochip)) & (1 << pin); |
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if (!u) { |
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return -EINVAL; |
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} |
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|
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type &= IRQ_TYPE_SENSE_MASK; |
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if (type == IRQ_TYPE_NONE) |
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return -EINVAL; |
|
|
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/* Check if we need to change chip and handler */ |
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if (!(ct->type & type)) |
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if (irq_setup_alt_chip(d, type)) |
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return -EINVAL; |
|
|
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/* |
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* Configure interrupt polarity. |
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*/ |
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) { |
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u = readl(GPIO_IN_POL(ochip)); |
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u &= ~(1 << pin); |
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writel(u, GPIO_IN_POL(ochip)); |
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} else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) { |
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u = readl(GPIO_IN_POL(ochip)); |
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u |= 1 << pin; |
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writel(u, GPIO_IN_POL(ochip)); |
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} else if (type == IRQ_TYPE_EDGE_BOTH) { |
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u32 v; |
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|
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v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip)); |
|
|
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/* |
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* set initial polarity based on current input level |
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*/ |
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u = readl(GPIO_IN_POL(ochip)); |
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if (v & (1 << pin)) |
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u |= 1 << pin; /* falling */ |
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else |
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u &= ~(1 << pin); /* rising */ |
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writel(u, GPIO_IN_POL(ochip)); |
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} |
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return 0; |
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} |
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|
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static void gpio_irq_handler(struct irq_desc *desc) |
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{ |
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struct orion_gpio_chip *ochip = irq_desc_get_handler_data(desc); |
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u32 cause, type; |
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int i; |
|
|
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if (ochip == NULL) |
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return; |
|
|
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cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip)); |
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cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip)); |
|
|
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for (i = 0; i < ochip->chip.ngpio; i++) { |
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int irq; |
|
|
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irq = ochip->secondary_irq_base + i; |
|
|
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if (!(cause & (1 << i))) |
|
continue; |
|
|
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type = irq_get_trigger_type(irq); |
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if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { |
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/* Swap polarity (race with GPIO line) */ |
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u32 polarity; |
|
|
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polarity = readl(GPIO_IN_POL(ochip)); |
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polarity ^= 1 << i; |
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writel(polarity, GPIO_IN_POL(ochip)); |
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} |
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generic_handle_irq(irq); |
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} |
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} |
|
|
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#ifdef CONFIG_DEBUG_FS |
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#include <linux/seq_file.h> |
|
|
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static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) |
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{ |
|
|
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struct orion_gpio_chip *ochip = gpiochip_get_data(chip); |
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u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; |
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const char *label; |
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int i; |
|
|
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out = readl_relaxed(GPIO_OUT(ochip)); |
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io_conf = readl_relaxed(GPIO_IO_CONF(ochip)); |
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blink = readl_relaxed(GPIO_BLINK_EN(ochip)); |
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in_pol = readl_relaxed(GPIO_IN_POL(ochip)); |
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data_in = readl_relaxed(GPIO_DATA_IN(ochip)); |
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cause = readl_relaxed(GPIO_EDGE_CAUSE(ochip)); |
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edg_msk = readl_relaxed(GPIO_EDGE_MASK(ochip)); |
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lvl_msk = readl_relaxed(GPIO_LEVEL_MASK(ochip)); |
|
|
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for_each_requested_gpio(chip, i, label) { |
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u32 msk; |
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bool is_out; |
|
|
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msk = 1 << i; |
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is_out = !(io_conf & msk); |
|
|
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seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); |
|
|
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if (is_out) { |
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seq_printf(s, " out %s %s\n", |
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out & msk ? "hi" : "lo", |
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blink & msk ? "(blink )" : ""); |
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continue; |
|
} |
|
|
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seq_printf(s, " in %s (act %s) - IRQ", |
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(data_in ^ in_pol) & msk ? "hi" : "lo", |
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in_pol & msk ? "lo" : "hi"); |
|
if (!((edg_msk | lvl_msk) & msk)) { |
|
seq_puts(s, " disabled\n"); |
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continue; |
|
} |
|
if (edg_msk & msk) |
|
seq_puts(s, " edge "); |
|
if (lvl_msk & msk) |
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seq_puts(s, " level"); |
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seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); |
|
} |
|
} |
|
#else |
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#define orion_gpio_dbg_show NULL |
|
#endif |
|
|
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static void orion_gpio_unmask_irq(struct irq_data *d) |
|
{ |
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
|
struct irq_chip_type *ct = irq_data_get_chip_type(d); |
|
u32 reg_val; |
|
u32 mask = d->mask; |
|
|
|
irq_gc_lock(gc); |
|
reg_val = irq_reg_readl(gc, ct->regs.mask); |
|
reg_val |= mask; |
|
irq_reg_writel(gc, reg_val, ct->regs.mask); |
|
irq_gc_unlock(gc); |
|
} |
|
|
|
static void orion_gpio_mask_irq(struct irq_data *d) |
|
{ |
|
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
|
struct irq_chip_type *ct = irq_data_get_chip_type(d); |
|
u32 mask = d->mask; |
|
u32 reg_val; |
|
|
|
irq_gc_lock(gc); |
|
reg_val = irq_reg_readl(gc, ct->regs.mask); |
|
reg_val &= ~mask; |
|
irq_reg_writel(gc, reg_val, ct->regs.mask); |
|
irq_gc_unlock(gc); |
|
} |
|
|
|
void __init orion_gpio_init(struct device_node *np, |
|
int gpio_base, int ngpio, |
|
void __iomem *base, int mask_offset, |
|
int secondary_irq_base, |
|
int irqs[4]) |
|
{ |
|
struct orion_gpio_chip *ochip; |
|
struct irq_chip_generic *gc; |
|
struct irq_chip_type *ct; |
|
char gc_label[16]; |
|
int i; |
|
|
|
if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips)) |
|
return; |
|
|
|
snprintf(gc_label, sizeof(gc_label), "orion_gpio%d", |
|
orion_gpio_chip_count); |
|
|
|
ochip = orion_gpio_chips + orion_gpio_chip_count; |
|
ochip->chip.label = kstrdup(gc_label, GFP_KERNEL); |
|
ochip->chip.request = orion_gpio_request; |
|
ochip->chip.direction_input = orion_gpio_direction_input; |
|
ochip->chip.get = orion_gpio_get; |
|
ochip->chip.direction_output = orion_gpio_direction_output; |
|
ochip->chip.set = orion_gpio_set; |
|
ochip->chip.to_irq = orion_gpio_to_irq; |
|
ochip->chip.base = gpio_base; |
|
ochip->chip.ngpio = ngpio; |
|
ochip->chip.can_sleep = 0; |
|
#ifdef CONFIG_OF |
|
ochip->chip.of_node = np; |
|
#endif |
|
ochip->chip.dbg_show = orion_gpio_dbg_show; |
|
|
|
spin_lock_init(&ochip->lock); |
|
ochip->base = (void __iomem *)base; |
|
ochip->valid_input = 0; |
|
ochip->valid_output = 0; |
|
ochip->mask_offset = mask_offset; |
|
ochip->secondary_irq_base = secondary_irq_base; |
|
|
|
gpiochip_add_data(&ochip->chip, ochip); |
|
|
|
/* |
|
* Mask and clear GPIO interrupts. |
|
*/ |
|
writel(0, GPIO_EDGE_CAUSE(ochip)); |
|
writel(0, GPIO_EDGE_MASK(ochip)); |
|
writel(0, GPIO_LEVEL_MASK(ochip)); |
|
|
|
/* Setup the interrupt handlers. Each chip can have up to 4 |
|
* interrupt handlers, with each handler dealing with 8 GPIO |
|
* pins. */ |
|
|
|
for (i = 0; i < 4; i++) { |
|
if (irqs[i]) { |
|
irq_set_chained_handler_and_data(irqs[i], |
|
gpio_irq_handler, |
|
ochip); |
|
} |
|
} |
|
|
|
gc = irq_alloc_generic_chip("orion_gpio_irq", 2, |
|
secondary_irq_base, |
|
ochip->base, handle_level_irq); |
|
gc->private = ochip; |
|
ct = gc->chip_types; |
|
ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF; |
|
ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; |
|
ct->chip.irq_mask = orion_gpio_mask_irq; |
|
ct->chip.irq_unmask = orion_gpio_unmask_irq; |
|
ct->chip.irq_set_type = gpio_irq_set_type; |
|
ct->chip.name = ochip->chip.label; |
|
|
|
ct++; |
|
ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF; |
|
ct->regs.ack = GPIO_EDGE_CAUSE_OFF; |
|
ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
|
ct->chip.irq_ack = irq_gc_ack_clr_bit; |
|
ct->chip.irq_mask = orion_gpio_mask_irq; |
|
ct->chip.irq_unmask = orion_gpio_unmask_irq; |
|
ct->chip.irq_set_type = gpio_irq_set_type; |
|
ct->handler = handle_edge_irq; |
|
ct->chip.name = ochip->chip.label; |
|
|
|
irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE, |
|
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); |
|
|
|
/* Setup irq domain on top of the generic chip. */ |
|
ochip->domain = irq_domain_add_legacy(np, |
|
ochip->chip.ngpio, |
|
ochip->secondary_irq_base, |
|
ochip->secondary_irq_base, |
|
&irq_domain_simple_ops, |
|
ochip); |
|
if (!ochip->domain) |
|
panic("%s: couldn't allocate irq domain (DT).\n", |
|
ochip->chip.label); |
|
|
|
orion_gpio_chip_count++; |
|
}
|
|
|