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59 lines
1.4 KiB
59 lines
1.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mm/tlbv4.S |
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* |
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* Copyright (C) 1997-2002 Russell King |
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* |
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* ARM architecture version 4 TLB handling functions. |
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* These assume a split I/D TLBs, and no write buffer. |
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* |
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* Processors: ARM720T |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <asm/assembler.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/tlbflush.h> |
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#include "proc-macros.S" |
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.align 5 |
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/* |
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* v4_flush_user_tlb_range(start, end, mm) |
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* |
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* Invalidate a range of TLB entries in the specified user address space. |
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* |
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* - start - range start address |
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* - end - range end address |
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* - mm - mm_struct describing address space |
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*/ |
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.align 5 |
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ENTRY(v4_flush_user_tlb_range) |
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vma_vm_mm ip, r2 |
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act_mm r3 @ get current->active_mm |
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eors r3, ip, r3 @ == mm ? |
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retne lr @ no, we dont do anything |
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.v4_flush_kern_tlb_range: |
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bic r0, r0, #0x0ff |
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bic r0, r0, #0xf00 |
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1: mcr p15, 0, r0, c8, c7, 1 @ invalidate TLB entry |
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add r0, r0, #PAGE_SZ |
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cmp r0, r1 |
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blo 1b |
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ret lr |
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/* |
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* v4_flush_kern_tlb_range(start, end) |
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* |
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* Invalidate a range of TLB entries in the specified kernel |
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* address range. |
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* |
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* - start - virtual address (may not be aligned) |
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* - end - virtual address (may not be aligned) |
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*/ |
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.globl v4_flush_kern_tlb_range |
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.equ v4_flush_kern_tlb_range, .v4_flush_kern_tlb_range |
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__INITDATA |
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/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ |
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define_tlb_functions v4, v4_tlb_flags
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