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658 lines
18 KiB
658 lines
18 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mm/proc-xscale.S |
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* |
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* Author: Nicolas Pitre |
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* Created: November 2000 |
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* Copyright: (C) 2000, 2001 MontaVista Software Inc. |
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* |
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* MMU functions for the Intel XScale CPUs |
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* |
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* 2001 Aug 21: |
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* some contributions by Brett Gaines <brett.w.gaines@intel.com> |
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* Copyright 2001 by Intel Corp. |
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* |
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* 2001 Sep 08: |
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* Completely revisited, many important fixes |
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* Nicolas Pitre <nico@fluxnic.net> |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/assembler.h> |
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#include <asm/hwcap.h> |
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#include <asm/pgtable-hwdef.h> |
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#include <asm/page.h> |
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#include <asm/ptrace.h> |
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#include "proc-macros.S" |
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/* |
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* This is the maximum size of an area which will be flushed. If the area |
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* is larger than this, then we flush the whole cache |
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*/ |
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#define MAX_AREA_SIZE 32768 |
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|
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/* |
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* the cache line size of the I and D cache |
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*/ |
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#define CACHELINESIZE 32 |
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|
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/* |
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* the size of the data cache |
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*/ |
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#define CACHESIZE 32768 |
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|
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/* |
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* Virtual address used to allocate the cache when flushed |
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* |
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* This must be an address range which is _never_ used. It should |
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* apparently have a mapping in the corresponding page table for |
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* compatibility with future CPUs that _could_ require it. For instance we |
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* don't care. |
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* |
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* This must be aligned on a 2*CACHESIZE boundary. The code selects one of |
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* the 2 areas in alternance each time the clean_d_cache macro is used. |
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* Without this the XScale core exhibits cache eviction problems and no one |
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* knows why. |
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* |
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* Reminder: the vector table is located at 0xffff0000-0xffff0fff. |
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*/ |
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#define CLEAN_ADDR 0xfffe0000 |
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/* |
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* This macro is used to wait for a CP15 write and is needed |
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* when we have to ensure that the last operation to the co-pro |
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* was completed before continuing with operation. |
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*/ |
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.macro cpwait, rd |
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 |
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mov \rd, \rd @ wait for completion |
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sub pc, pc, #4 @ flush instruction pipeline |
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.endm |
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.macro cpwait_ret, lr, rd |
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mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 |
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sub pc, \lr, \rd, LSR #32 @ wait for completion and |
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@ flush instruction pipeline |
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.endm |
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/* |
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* This macro cleans the entire dcache using line allocate. |
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* The main loop has been unrolled to reduce loop overhead. |
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* rd and rs are two scratch registers. |
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*/ |
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.macro clean_d_cache, rd, rs |
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ldr \rs, =clean_addr |
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ldr \rd, [\rs] |
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eor \rd, \rd, #CACHESIZE |
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str \rd, [\rs] |
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add \rs, \rd, #CACHESIZE |
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1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line |
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add \rd, \rd, #CACHELINESIZE |
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line |
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add \rd, \rd, #CACHELINESIZE |
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line |
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add \rd, \rd, #CACHELINESIZE |
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mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line |
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add \rd, \rd, #CACHELINESIZE |
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teq \rd, \rs |
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bne 1b |
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.endm |
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.data |
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.align 2 |
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clean_addr: .word CLEAN_ADDR |
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.text |
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/* |
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* cpu_xscale_proc_init() |
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* |
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* Nothing too exciting at the moment |
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*/ |
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ENTRY(cpu_xscale_proc_init) |
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@ enable write buffer coalescing. Some bootloader disable it |
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mrc p15, 0, r1, c1, c0, 1 |
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bic r1, r1, #1 |
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mcr p15, 0, r1, c1, c0, 1 |
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ret lr |
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/* |
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* cpu_xscale_proc_fin() |
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*/ |
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ENTRY(cpu_xscale_proc_fin) |
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
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bic r0, r0, #0x1800 @ ...IZ........... |
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bic r0, r0, #0x0006 @ .............CA. |
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mcr p15, 0, r0, c1, c0, 0 @ disable caches |
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ret lr |
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/* |
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* cpu_xscale_reset(loc) |
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* |
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* Perform a soft reset of the system. Put the CPU into the |
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* same state as it would be if it had been reset, and branch |
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* to what would be the reset vector. |
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* |
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* loc: location to jump to for soft reset |
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* |
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* Beware PXA270 erratum E7. |
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*/ |
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.align 5 |
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.pushsection .idmap.text, "ax" |
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ENTRY(cpu_xscale_reset) |
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mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE |
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msr cpsr_c, r1 @ reset CPSR |
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mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB |
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mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB |
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
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bic r1, r1, #0x0086 @ ........B....CA. |
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bic r1, r1, #0x3900 @ ..VIZ..S........ |
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sub pc, pc, #4 @ flush pipeline |
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@ *** cache line aligned *** |
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register |
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bic r1, r1, #0x0001 @ ...............M |
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB |
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mcr p15, 0, r1, c1, c0, 0 @ ctrl register |
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@ CAUTION: MMU turned off from this point. We count on the pipeline |
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@ already containing those two last instructions to survive. |
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
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ret r0 |
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ENDPROC(cpu_xscale_reset) |
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.popsection |
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/* |
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* cpu_xscale_do_idle() |
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* |
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* Cause the processor to idle |
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* |
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* For now we do nothing but go to idle mode for every case |
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* |
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* XScale supports clock switching, but using idle mode support |
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* allows external hardware to react to system state changes. |
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*/ |
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.align 5 |
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ENTRY(cpu_xscale_do_idle) |
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mov r0, #1 |
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mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE |
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ret lr |
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/* ================================= CACHE ================================ */ |
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/* |
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* flush_icache_all() |
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* |
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* Unconditionally clean and invalidate the entire icache. |
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*/ |
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ENTRY(xscale_flush_icache_all) |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache |
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ret lr |
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ENDPROC(xscale_flush_icache_all) |
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/* |
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* flush_user_cache_all() |
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* |
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* Invalidate all cache entries in a particular address |
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* space. |
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*/ |
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ENTRY(xscale_flush_user_cache_all) |
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/* FALLTHROUGH */ |
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/* |
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* flush_kern_cache_all() |
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* |
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* Clean and invalidate the entire cache. |
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*/ |
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ENTRY(xscale_flush_kern_cache_all) |
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mov r2, #VM_EXEC |
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mov ip, #0 |
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__flush_whole_cache: |
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clean_d_cache r0, r1 |
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tst r2, #VM_EXEC |
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mcrne p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB |
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* flush_user_cache_range(start, end, vm_flags) |
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* |
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* Invalidate a range of cache entries in the specified |
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* address space. |
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* |
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* - start - start address (may not be aligned) |
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* - end - end address (exclusive, may not be aligned) |
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* - vma - vma_area_struct describing address space |
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*/ |
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.align 5 |
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ENTRY(xscale_flush_user_cache_range) |
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mov ip, #0 |
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sub r3, r1, r0 @ calculate total size |
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cmp r3, #MAX_AREA_SIZE |
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bhs __flush_whole_cache |
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1: tst r2, #VM_EXEC |
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mcrne p15, 0, r0, c7, c5, 1 @ Invalidate I cache line |
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mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line |
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mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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tst r2, #VM_EXEC |
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mcrne p15, 0, ip, c7, c5, 6 @ Invalidate BTB |
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mcrne p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* coherent_kern_range(start, end) |
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* |
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* Ensure coherency between the Icache and the Dcache in the |
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* region described by start. If you have non-snooping |
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* Harvard caches, you need to implement this function. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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* |
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* Note: single I-cache line invalidation isn't used here since |
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* it also trashes the mini I-cache used by JTAG debuggers. |
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*/ |
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ENTRY(xscale_coherent_kern_range) |
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bic r0, r0, #CACHELINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* coherent_user_range(start, end) |
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* |
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* Ensure coherency between the Icache and the Dcache in the |
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* region described by start. If you have non-snooping |
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* Harvard caches, you need to implement this function. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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*/ |
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ENTRY(xscale_coherent_user_range) |
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bic r0, r0, #CACHELINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* flush_kern_dcache_area(void *addr, size_t size) |
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* |
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* Ensure no D cache aliasing occurs, either with itself or |
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* the I cache |
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* |
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* - addr - kernel address |
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* - size - region size |
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*/ |
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ENTRY(xscale_flush_kern_dcache_area) |
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add r1, r0, r1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* dma_inv_range(start, end) |
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* |
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* Invalidate (discard) the specified virtual address range. |
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* May not write back any entries. If 'start' or 'end' |
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* are not cache line aligned, those lines must be written |
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* back. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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*/ |
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xscale_dma_inv_range: |
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tst r0, #CACHELINESIZE - 1 |
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bic r0, r0, #CACHELINESIZE - 1 |
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mcrne p15, 0, r0, c7, c10, 1 @ clean D entry |
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tst r1, #CACHELINESIZE - 1 |
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mcrne p15, 0, r1, c7, c10, 1 @ clean D entry |
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1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* dma_clean_range(start, end) |
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* |
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* Clean the specified virtual address range. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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*/ |
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xscale_dma_clean_range: |
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bic r0, r0, #CACHELINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* dma_flush_range(start, end) |
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* |
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* Clean and invalidate the specified virtual address range. |
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* |
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* - start - virtual start address |
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* - end - virtual end address |
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*/ |
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ENTRY(xscale_dma_flush_range) |
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bic r0, r0, #CACHELINESIZE - 1 |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry |
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add r0, r0, #CACHELINESIZE |
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cmp r0, r1 |
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blo 1b |
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mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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ret lr |
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/* |
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* dma_map_area(start, size, dir) |
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* - start - kernel virtual start address |
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* - size - size of region |
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* - dir - DMA direction |
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*/ |
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ENTRY(xscale_dma_map_area) |
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add r1, r1, r0 |
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cmp r2, #DMA_TO_DEVICE |
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beq xscale_dma_clean_range |
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bcs xscale_dma_inv_range |
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b xscale_dma_flush_range |
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ENDPROC(xscale_dma_map_area) |
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/* |
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* dma_map_area(start, size, dir) |
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* - start - kernel virtual start address |
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* - size - size of region |
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* - dir - DMA direction |
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*/ |
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ENTRY(xscale_80200_A0_A1_dma_map_area) |
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add r1, r1, r0 |
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teq r2, #DMA_TO_DEVICE |
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beq xscale_dma_clean_range |
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b xscale_dma_flush_range |
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ENDPROC(xscale_80200_A0_A1_dma_map_area) |
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/* |
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* dma_unmap_area(start, size, dir) |
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* - start - kernel virtual start address |
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* - size - size of region |
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* - dir - DMA direction |
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*/ |
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ENTRY(xscale_dma_unmap_area) |
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ret lr |
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ENDPROC(xscale_dma_unmap_area) |
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.globl xscale_flush_kern_cache_louis |
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.equ xscale_flush_kern_cache_louis, xscale_flush_kern_cache_all |
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
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define_cache_functions xscale |
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/* |
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* On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't |
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* clear the dirty bits, which means that if we invalidate a dirty line, |
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* the dirty data can still be written back to external memory later on. |
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* |
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* The recommended workaround is to always do a clean D-cache line before |
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* doing an invalidate D-cache line, so on the affected processors, |
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* dma_inv_range() is implemented as dma_flush_range(). |
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* |
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* See erratum #25 of "Intel 80200 Processor Specification Update", |
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* revision January 22, 2003, available at: |
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* http://www.intel.com/design/iio/specupdt/273415.htm |
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*/ |
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.macro a0_alias basename |
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.globl xscale_80200_A0_A1_\basename |
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.type xscale_80200_A0_A1_\basename , %function |
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.equ xscale_80200_A0_A1_\basename , xscale_\basename |
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.endm |
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/* |
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* Most of the cache functions are unchanged for these processor revisions. |
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* Export suitable alias symbols for the unchanged functions: |
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*/ |
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a0_alias flush_icache_all |
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a0_alias flush_user_cache_all |
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a0_alias flush_kern_cache_all |
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a0_alias flush_kern_cache_louis |
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a0_alias flush_user_cache_range |
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a0_alias coherent_kern_range |
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a0_alias coherent_user_range |
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a0_alias flush_kern_dcache_area |
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a0_alias dma_flush_range |
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a0_alias dma_unmap_area |
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S) |
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define_cache_functions xscale_80200_A0_A1 |
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ENTRY(cpu_xscale_dcache_clean_area) |
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry |
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add r0, r0, #CACHELINESIZE |
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subs r1, r1, #CACHELINESIZE |
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bhi 1b |
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ret lr |
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/* =============================== PageTable ============================== */ |
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/* |
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* cpu_xscale_switch_mm(pgd) |
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* |
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* Set the translation base pointer to be as described by pgd. |
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* |
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* pgd: new page tables |
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*/ |
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.align 5 |
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ENTRY(cpu_xscale_switch_mm) |
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clean_d_cache r1, r2 |
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mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB |
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
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cpwait_ret lr, ip |
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/* |
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* cpu_xscale_set_pte_ext(ptep, pte, ext) |
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* |
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* Set a PTE and flush it out |
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* |
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* Errata 40: must set memory to write-through for user read-only pages. |
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*/ |
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cpu_xscale_mt_table: |
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.long 0x00 @ L_PTE_MT_UNCACHED |
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.long PTE_BUFFERABLE @ L_PTE_MT_BUFFERABLE |
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH |
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK |
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.long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED |
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.long 0x00 @ unused |
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE @ L_PTE_MT_MINICACHE |
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC |
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.long 0x00 @ unused |
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_WC |
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.long 0x00 @ unused |
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED |
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.long 0x00 @ L_PTE_MT_DEV_NONSHARED |
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.long 0x00 @ unused |
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.long 0x00 @ unused |
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.long 0x00 @ unused |
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.align 5 |
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ENTRY(cpu_xscale_set_pte_ext) |
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xscale_set_pte_ext_prologue |
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@ |
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@ Erratum 40: must set memory to write-through for user read-only pages |
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@ |
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and ip, r1, #(L_PTE_MT_MASK | L_PTE_USER | L_PTE_RDONLY) & ~(4 << 2) |
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teq ip, #L_PTE_MT_WRITEBACK | L_PTE_USER | L_PTE_RDONLY |
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moveq r1, #L_PTE_MT_WRITETHROUGH |
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and r1, r1, #L_PTE_MT_MASK |
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adr ip, cpu_xscale_mt_table |
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ldr ip, [ip, r1] |
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bic r2, r2, #0x0c |
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orr r2, r2, ip |
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xscale_set_pte_ext_epilogue |
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ret lr |
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.ltorg |
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.align |
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.globl cpu_xscale_suspend_size |
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.equ cpu_xscale_suspend_size, 4 * 6 |
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#ifdef CONFIG_ARM_CPU_SUSPEND |
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ENTRY(cpu_xscale_do_suspend) |
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stmfd sp!, {r4 - r9, lr} |
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mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode |
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mrc p15, 0, r5, c15, c1, 0 @ CP access reg |
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mrc p15, 0, r6, c13, c0, 0 @ PID |
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mrc p15, 0, r7, c3, c0, 0 @ domain ID |
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mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg |
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mrc p15, 0, r9, c1, c0, 0 @ control reg |
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bic r4, r4, #2 @ clear frequency change bit |
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stmia r0, {r4 - r9} @ store cp regs |
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ldmfd sp!, {r4 - r9, pc} |
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ENDPROC(cpu_xscale_do_suspend) |
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|
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ENTRY(cpu_xscale_do_resume) |
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ldmia r0, {r4 - r9} @ load cp regs |
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mov ip, #0 |
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB |
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mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode. |
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mcr p15, 0, r5, c15, c1, 0 @ CP access reg |
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mcr p15, 0, r6, c13, c0, 0 @ PID |
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mcr p15, 0, r7, c3, c0, 0 @ domain ID |
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mcr p15, 0, r1, c2, c0, 0 @ translation table base addr |
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mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg |
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mov r0, r9 @ control register |
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b cpu_resume_mmu |
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ENDPROC(cpu_xscale_do_resume) |
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#endif |
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|
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.type __xscale_setup, #function |
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__xscale_setup: |
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mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB |
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mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer |
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mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs |
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mov r0, #1 << 6 @ cp6 for IOP3xx and Bulverde |
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orr r0, r0, #1 << 13 @ Its undefined whether this |
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mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes |
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|
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adr r5, xscale_crval |
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ldmia r5, {r5, r6} |
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mrc p15, 0, r0, c1, c0, 0 @ get control register |
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bic r0, r0, r5 |
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orr r0, r0, r6 |
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ret lr |
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.size __xscale_setup, . - __xscale_setup |
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|
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/* |
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* R |
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* .RVI ZFRS BLDP WCAM |
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* ..11 1.01 .... .101 |
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* |
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*/ |
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.type xscale_crval, #object |
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xscale_crval: |
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crval clear=0x00003b07, mmuset=0x00003905, ucset=0x00001900 |
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|
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__INITDATA |
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|
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
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define_processor_functions xscale, dabort=v5t_early_abort, pabort=legacy_pabort, suspend=1 |
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|
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.section ".rodata" |
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|
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string cpu_arch_name, "armv5te" |
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string cpu_elf_name, "v5" |
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|
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string cpu_80200_A0_A1_name, "XScale-80200 A0/A1" |
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string cpu_80200_name, "XScale-80200" |
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string cpu_80219_name, "XScale-80219" |
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string cpu_8032x_name, "XScale-IOP8032x Family" |
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string cpu_8033x_name, "XScale-IOP8033x Family" |
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string cpu_pxa250_name, "XScale-PXA250" |
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string cpu_pxa210_name, "XScale-PXA210" |
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string cpu_ixp42x_name, "XScale-IXP42x Family" |
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string cpu_ixp43x_name, "XScale-IXP43x Family" |
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string cpu_ixp46x_name, "XScale-IXP46x Family" |
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string cpu_ixp2400_name, "XScale-IXP2400" |
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string cpu_ixp2800_name, "XScale-IXP2800" |
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string cpu_pxa255_name, "XScale-PXA255" |
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string cpu_pxa270_name, "XScale-PXA270" |
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|
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.align |
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|
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.section ".proc.info.init", "a" |
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|
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.macro xscale_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cache |
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.type __\name\()_proc_info,#object |
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__\name\()_proc_info: |
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.long \cpu_val |
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.long \cpu_mask |
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.long PMD_TYPE_SECT | \ |
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PMD_SECT_BUFFERABLE | \ |
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PMD_SECT_CACHEABLE | \ |
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PMD_SECT_AP_WRITE | \ |
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PMD_SECT_AP_READ |
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.long PMD_TYPE_SECT | \ |
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PMD_SECT_AP_WRITE | \ |
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PMD_SECT_AP_READ |
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initfn __xscale_setup, __\name\()_proc_info |
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.long cpu_arch_name |
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.long cpu_elf_name |
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.long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP |
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.long \cpu_name |
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.long xscale_processor_functions |
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.long v4wbi_tlb_fns |
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.long xscale_mc_user_fns |
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.ifb \cache |
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.long xscale_cache_fns |
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.else |
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.long \cache |
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.endif |
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.size __\name\()_proc_info, . - __\name\()_proc_info |
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.endm |
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|
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xscale_proc_info 80200_A0_A1, 0x69052000, 0xfffffffe, cpu_80200_name, \ |
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cache=xscale_80200_A0_A1_cache_fns |
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xscale_proc_info 80200, 0x69052000, 0xfffffff0, cpu_80200_name |
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xscale_proc_info 80219, 0x69052e20, 0xffffffe0, cpu_80219_name |
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xscale_proc_info 8032x, 0x69052420, 0xfffff7e0, cpu_8032x_name |
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xscale_proc_info 8033x, 0x69054010, 0xfffffd30, cpu_8033x_name |
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xscale_proc_info pxa250, 0x69052100, 0xfffff7f0, cpu_pxa250_name |
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xscale_proc_info pxa210, 0x69052120, 0xfffff3f0, cpu_pxa210_name |
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xscale_proc_info ixp2400, 0x69054190, 0xfffffff0, cpu_ixp2400_name |
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xscale_proc_info ixp2800, 0x690541a0, 0xfffffff0, cpu_ixp2800_name |
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xscale_proc_info ixp42x, 0x690541c0, 0xffffffc0, cpu_ixp42x_name |
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xscale_proc_info ixp43x, 0x69054040, 0xfffffff0, cpu_ixp43x_name |
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xscale_proc_info ixp46x, 0x69054200, 0xffffff00, cpu_ixp46x_name |
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xscale_proc_info pxa255, 0x69052d00, 0xfffffff0, cpu_pxa255_name |
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xscale_proc_info pxa270, 0x69054110, 0xfffffff0, cpu_pxa270_name
|
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|