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235 lines
6.0 KiB
235 lines
6.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mm/proc-v7m.S |
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* |
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* Copyright (C) 2008 ARM Ltd. |
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* Copyright (C) 2001 Deep Blue Solutions Ltd. |
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* |
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* This is the "shell" of the ARMv7-M processor support. |
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*/ |
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#include <linux/linkage.h> |
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#include <asm/assembler.h> |
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#include <asm/memory.h> |
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#include <asm/v7m.h> |
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#include "proc-macros.S" |
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ENTRY(cpu_v7m_proc_init) |
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ret lr |
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ENDPROC(cpu_v7m_proc_init) |
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ENTRY(cpu_v7m_proc_fin) |
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ret lr |
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ENDPROC(cpu_v7m_proc_fin) |
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/* |
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* cpu_v7m_reset(loc) |
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* |
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* Perform a soft reset of the system. Put the CPU into the |
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* same state as it would be if it had been reset, and branch |
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* to what would be the reset vector. |
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* |
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* - loc - location to jump to for soft reset |
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*/ |
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.align 5 |
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ENTRY(cpu_v7m_reset) |
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ret r0 |
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ENDPROC(cpu_v7m_reset) |
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/* |
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* cpu_v7m_do_idle() |
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* |
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* Idle the processor (eg, wait for interrupt). |
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* |
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* IRQs are already disabled. |
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*/ |
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ENTRY(cpu_v7m_do_idle) |
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wfi |
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ret lr |
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ENDPROC(cpu_v7m_do_idle) |
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ENTRY(cpu_v7m_dcache_clean_area) |
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ret lr |
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ENDPROC(cpu_v7m_dcache_clean_area) |
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/* |
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* There is no MMU, so here is nothing to do. |
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*/ |
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ENTRY(cpu_v7m_switch_mm) |
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ret lr |
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ENDPROC(cpu_v7m_switch_mm) |
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.globl cpu_v7m_suspend_size |
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.equ cpu_v7m_suspend_size, 0 |
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#ifdef CONFIG_ARM_CPU_SUSPEND |
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ENTRY(cpu_v7m_do_suspend) |
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ret lr |
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ENDPROC(cpu_v7m_do_suspend) |
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ENTRY(cpu_v7m_do_resume) |
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ret lr |
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ENDPROC(cpu_v7m_do_resume) |
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#endif |
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ENTRY(cpu_cm7_dcache_clean_area) |
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dcache_line_size r2, r3 |
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movw r3, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC |
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movt r3, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_DCCMVAC |
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1: str r0, [r3] @ clean D entry |
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add r0, r0, r2 |
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subs r1, r1, r2 |
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bhi 1b |
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dsb |
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ret lr |
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ENDPROC(cpu_cm7_dcache_clean_area) |
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ENTRY(cpu_cm7_proc_fin) |
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movw r2, #:lower16:(BASEADDR_V7M_SCB + V7M_SCB_CCR) |
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movt r2, #:upper16:(BASEADDR_V7M_SCB + V7M_SCB_CCR) |
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ldr r0, [r2] |
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bic r0, r0, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC) |
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str r0, [r2] |
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ret lr |
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ENDPROC(cpu_cm7_proc_fin) |
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.section ".init.text", "ax" |
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__v7m_cm7_setup: |
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mov r8, #(V7M_SCB_CCR_DC | V7M_SCB_CCR_IC| V7M_SCB_CCR_BP) |
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b __v7m_setup_cont |
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/* |
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* __v7m_setup |
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* |
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* This should be able to cover all ARMv7-M cores. |
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*/ |
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__v7m_setup: |
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mov r8, 0 |
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__v7m_setup_cont: |
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@ Configure the vector table base address |
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ldr r0, =BASEADDR_V7M_SCB |
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ldr r12, =vector_table |
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str r12, [r0, V7M_SCB_VTOR] |
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@ enable UsageFault, BusFault and MemManage fault. |
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ldr r5, [r0, #V7M_SCB_SHCSR] |
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orr r5, #(V7M_SCB_SHCSR_USGFAULTENA | V7M_SCB_SHCSR_BUSFAULTENA | V7M_SCB_SHCSR_MEMFAULTENA) |
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str r5, [r0, #V7M_SCB_SHCSR] |
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@ Lower the priority of the SVC and PendSV exceptions |
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mov r5, #0x80000000 |
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str r5, [r0, V7M_SCB_SHPR2] @ set SVC priority |
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mov r5, #0x00800000 |
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str r5, [r0, V7M_SCB_SHPR3] @ set PendSV priority |
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@ SVC to switch to handler mode. Notice that this requires sp to |
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@ point to writeable memory because the processor saves |
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@ some registers to the stack. |
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badr r1, 1f |
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ldr r5, [r12, #11 * 4] @ read the SVC vector entry |
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str r1, [r12, #11 * 4] @ write the temporary SVC vector entry |
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dsb |
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mov r6, lr @ save LR |
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ldr sp, =init_thread_union + THREAD_START_SP |
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cpsie i |
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svc #0 |
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1: cpsid i |
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/* Calculate exc_ret */ |
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orr r10, lr, #EXC_RET_THREADMODE_PROCESSSTACK |
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ldmia sp, {r0-r3, r12} |
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str r5, [r12, #11 * 4] @ restore the original SVC vector entry |
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mov lr, r6 @ restore LR |
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@ Special-purpose control register |
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mov r1, #1 |
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msr control, r1 @ Thread mode has unpriviledged access |
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@ Configure caches (if implemented) |
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teq r8, #0 |
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stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6 |
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blne v7m_invalidate_l1 |
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teq r8, #0 @ re-evalutae condition |
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ldmiane sp, {r0-r6, lr} |
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@ Configure the System Control Register to ensure 8-byte stack alignment |
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@ Note the STKALIGN bit is either RW or RAO. |
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ldr r0, [r0, V7M_SCB_CCR] @ system control register |
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orr r0, #V7M_SCB_CCR_STKALIGN |
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orr r0, r0, r8 |
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ret lr |
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ENDPROC(__v7m_setup) |
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/* |
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* Cortex-M7 processor functions |
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*/ |
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globl_equ cpu_cm7_proc_init, cpu_v7m_proc_init |
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globl_equ cpu_cm7_reset, cpu_v7m_reset |
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globl_equ cpu_cm7_do_idle, cpu_v7m_do_idle |
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globl_equ cpu_cm7_switch_mm, cpu_v7m_switch_mm |
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define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1 |
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define_processor_functions cm7, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1 |
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.section ".rodata" |
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string cpu_arch_name, "armv7m" |
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string cpu_elf_name "v7m" |
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string cpu_v7m_name "ARMv7-M" |
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.section ".proc.info.init", "a" |
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.macro __v7m_proc name, initfunc, cache_fns = nop_cache_fns, hwcaps = 0, proc_fns = v7m_processor_functions |
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.long 0 /* proc_info_list.__cpu_mm_mmu_flags */ |
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.long 0 /* proc_info_list.__cpu_io_mmu_flags */ |
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initfn \initfunc, \name |
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.long cpu_arch_name |
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.long cpu_elf_name |
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.long HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \hwcaps |
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.long cpu_v7m_name |
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.long \proc_fns |
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.long 0 /* proc_info_list.tlb */ |
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.long 0 /* proc_info_list.user */ |
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.long \cache_fns |
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.endm |
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/* |
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* Match ARM Cortex-M7 processor. |
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*/ |
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.type __v7m_cm7_proc_info, #object |
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__v7m_cm7_proc_info: |
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.long 0x410fc270 /* ARM Cortex-M7 0xC27 */ |
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.long 0xff0ffff0 /* Mask off revision, patch release */ |
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__v7m_proc __v7m_cm7_proc_info, __v7m_cm7_setup, hwcaps = HWCAP_EDSP, cache_fns = v7m_cache_fns, proc_fns = cm7_processor_functions |
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.size __v7m_cm7_proc_info, . - __v7m_cm7_proc_info |
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/* |
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* Match ARM Cortex-M4 processor. |
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*/ |
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.type __v7m_cm4_proc_info, #object |
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__v7m_cm4_proc_info: |
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.long 0x410fc240 /* ARM Cortex-M4 0xC24 */ |
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.long 0xff0ffff0 /* Mask off revision, patch release */ |
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__v7m_proc __v7m_cm4_proc_info, __v7m_setup, hwcaps = HWCAP_EDSP |
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.size __v7m_cm4_proc_info, . - __v7m_cm4_proc_info |
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/* |
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* Match ARM Cortex-M3 processor. |
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*/ |
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.type __v7m_cm3_proc_info, #object |
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__v7m_cm3_proc_info: |
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.long 0x410fc230 /* ARM Cortex-M3 0xC23 */ |
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.long 0xff0ffff0 /* Mask off revision, patch release */ |
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__v7m_proc __v7m_cm3_proc_info, __v7m_setup |
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.size __v7m_cm3_proc_info, . - __v7m_cm3_proc_info |
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/* |
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* Match any ARMv7-M processor core. |
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*/ |
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.type __v7m_proc_info, #object |
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__v7m_proc_info: |
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.long 0x000f0000 @ Required ID value |
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.long 0x000f0000 @ Mask for ID |
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__v7m_proc __v7m_proc_info, __v7m_setup |
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.size __v7m_proc_info, . - __v7m_proc_info |
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