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157 lines
3.7 KiB
157 lines
3.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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#include <linux/arm-smccc.h> |
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#include <linux/kernel.h> |
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#include <linux/smp.h> |
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#include <asm/cp15.h> |
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#include <asm/cputype.h> |
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#include <asm/proc-fns.h> |
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#include <asm/system_misc.h> |
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#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR |
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DEFINE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn); |
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extern void cpu_v7_iciallu_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); |
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extern void cpu_v7_bpiall_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); |
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extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); |
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extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm); |
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static void harden_branch_predictor_bpiall(void) |
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{ |
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write_sysreg(0, BPIALL); |
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} |
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static void harden_branch_predictor_iciallu(void) |
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{ |
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write_sysreg(0, ICIALLU); |
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} |
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static void __maybe_unused call_smc_arch_workaround_1(void) |
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{ |
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arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); |
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} |
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static void __maybe_unused call_hvc_arch_workaround_1(void) |
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{ |
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL); |
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} |
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static void cpu_v7_spectre_init(void) |
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{ |
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const char *spectre_v2_method = NULL; |
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int cpu = smp_processor_id(); |
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if (per_cpu(harden_branch_predictor_fn, cpu)) |
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return; |
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switch (read_cpuid_part()) { |
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case ARM_CPU_PART_CORTEX_A8: |
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case ARM_CPU_PART_CORTEX_A9: |
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case ARM_CPU_PART_CORTEX_A12: |
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case ARM_CPU_PART_CORTEX_A17: |
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case ARM_CPU_PART_CORTEX_A73: |
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case ARM_CPU_PART_CORTEX_A75: |
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per_cpu(harden_branch_predictor_fn, cpu) = |
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harden_branch_predictor_bpiall; |
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spectre_v2_method = "BPIALL"; |
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break; |
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case ARM_CPU_PART_CORTEX_A15: |
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case ARM_CPU_PART_BRAHMA_B15: |
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per_cpu(harden_branch_predictor_fn, cpu) = |
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harden_branch_predictor_iciallu; |
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spectre_v2_method = "ICIALLU"; |
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break; |
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#ifdef CONFIG_ARM_PSCI |
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case ARM_CPU_PART_BRAHMA_B53: |
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/* Requires no workaround */ |
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break; |
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default: |
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/* Other ARM CPUs require no workaround */ |
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if (read_cpuid_implementor() == ARM_CPU_IMP_ARM) |
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break; |
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fallthrough; |
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/* Cortex A57/A72 require firmware workaround */ |
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case ARM_CPU_PART_CORTEX_A57: |
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case ARM_CPU_PART_CORTEX_A72: { |
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struct arm_smccc_res res; |
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arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, |
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ARM_SMCCC_ARCH_WORKAROUND_1, &res); |
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if ((int)res.a0 != 0) |
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return; |
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switch (arm_smccc_1_1_get_conduit()) { |
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case SMCCC_CONDUIT_HVC: |
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per_cpu(harden_branch_predictor_fn, cpu) = |
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call_hvc_arch_workaround_1; |
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cpu_do_switch_mm = cpu_v7_hvc_switch_mm; |
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spectre_v2_method = "hypervisor"; |
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break; |
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case SMCCC_CONDUIT_SMC: |
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per_cpu(harden_branch_predictor_fn, cpu) = |
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call_smc_arch_workaround_1; |
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cpu_do_switch_mm = cpu_v7_smc_switch_mm; |
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spectre_v2_method = "firmware"; |
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break; |
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default: |
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break; |
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} |
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} |
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#endif |
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} |
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if (spectre_v2_method) |
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pr_info("CPU%u: Spectre v2: using %s workaround\n", |
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smp_processor_id(), spectre_v2_method); |
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} |
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#else |
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static void cpu_v7_spectre_init(void) |
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{ |
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} |
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#endif |
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static __maybe_unused bool cpu_v7_check_auxcr_set(bool *warned, |
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u32 mask, const char *msg) |
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{ |
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u32 aux_cr; |
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (aux_cr)); |
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if ((aux_cr & mask) != mask) { |
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if (!*warned) |
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pr_err("CPU%u: %s", smp_processor_id(), msg); |
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*warned = true; |
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return false; |
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} |
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return true; |
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} |
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static DEFINE_PER_CPU(bool, spectre_warned); |
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static bool check_spectre_auxcr(bool *warned, u32 bit) |
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{ |
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return IS_ENABLED(CONFIG_HARDEN_BRANCH_PREDICTOR) && |
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cpu_v7_check_auxcr_set(warned, bit, |
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"Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable\n"); |
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} |
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void cpu_v7_ca8_ibe(void) |
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{ |
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if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(6))) |
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cpu_v7_spectre_init(); |
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} |
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void cpu_v7_ca15_ibe(void) |
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{ |
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if (check_spectre_auxcr(this_cpu_ptr(&spectre_warned), BIT(0))) |
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cpu_v7_spectre_init(); |
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} |
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void cpu_v7_bugs_init(void) |
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{ |
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cpu_v7_spectre_init(); |
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}
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