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147 lines
3.7 KiB
147 lines
3.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mm/arm740.S: utility functions for ARM740 |
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* |
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com) |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/assembler.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/hwcap.h> |
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#include <asm/pgtable-hwdef.h> |
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#include <asm/ptrace.h> |
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#include "proc-macros.S" |
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.text |
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/* |
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* cpu_arm740_proc_init() |
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* cpu_arm740_do_idle() |
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* cpu_arm740_dcache_clean_area() |
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* cpu_arm740_switch_mm() |
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* |
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* These are not required. |
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*/ |
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ENTRY(cpu_arm740_proc_init) |
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ENTRY(cpu_arm740_do_idle) |
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ENTRY(cpu_arm740_dcache_clean_area) |
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ENTRY(cpu_arm740_switch_mm) |
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ret lr |
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/* |
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* cpu_arm740_proc_fin() |
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*/ |
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ENTRY(cpu_arm740_proc_fin) |
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mrc p15, 0, r0, c1, c0, 0 |
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bic r0, r0, #0x3f000000 @ bank/f/lock/s |
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bic r0, r0, #0x0000000c @ w-buffer/cache |
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mcr p15, 0, r0, c1, c0, 0 @ disable caches |
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ret lr |
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/* |
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* cpu_arm740_reset(loc) |
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* Params : r0 = address to jump to |
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* Notes : This sets up everything for a reset |
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*/ |
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.pushsection .idmap.text, "ax" |
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ENTRY(cpu_arm740_reset) |
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mov ip, #0 |
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mcr p15, 0, ip, c7, c0, 0 @ invalidate cache |
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register |
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bic ip, ip, #0x0000000c @ ............wc.. |
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
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ret r0 |
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ENDPROC(cpu_arm740_reset) |
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.popsection |
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.type __arm740_setup, #function |
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__arm740_setup: |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c0, 0 @ invalidate caches |
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mcr p15, 0, r0, c6, c3 @ disable area 3~7 |
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mcr p15, 0, r0, c6, c4 |
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mcr p15, 0, r0, c6, c5 |
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mcr p15, 0, r0, c6, c6 |
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mcr p15, 0, r0, c6, c7 |
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mov r0, #0x0000003F @ base = 0, size = 4GB |
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mcr p15, 0, r0, c6, c0 @ set area 0, default |
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM |
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ldr r3, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB) |
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mov r4, #10 @ 11 is the minimum (4KB) |
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1: add r4, r4, #1 @ area size *= 2 |
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movs r3, r3, lsr #1 |
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bne 1b @ count not zero r-shift |
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orr r0, r0, r4, lsl #1 @ the area register value |
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orr r0, r0, #1 @ set enable bit |
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mcr p15, 0, r0, c6, c1 @ set area 1, RAM |
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH |
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ldr r3, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB) |
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cmp r3, #0 |
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moveq r0, #0 |
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beq 2f |
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mov r4, #10 @ 11 is the minimum (4KB) |
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1: add r4, r4, #1 @ area size *= 2 |
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movs r3, r3, lsr #1 |
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bne 1b @ count not zero r-shift |
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orr r0, r0, r4, lsl #1 @ the area register value |
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orr r0, r0, #1 @ set enable bit |
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2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH |
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mov r0, #0x06 |
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mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable |
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH |
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mov r0, #0x00 @ disable whole write buffer |
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#else |
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mov r0, #0x02 @ Region 1 write bufferred |
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#endif |
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mcr p15, 0, r0, c3, c0 |
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mov r0, #0x10000 |
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sub r0, r0, #1 @ r0 = 0xffff |
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mcr p15, 0, r0, c5, c0 @ all read/write access |
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mrc p15, 0, r0, c1, c0 @ get control register |
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bic r0, r0, #0x3F000000 @ set to standard caching mode |
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@ need some benchmark |
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orr r0, r0, #0x0000000d @ MPU/Cache/WB |
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ret lr |
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.size __arm740_setup, . - __arm740_setup |
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__INITDATA |
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
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define_processor_functions arm740, dabort=v4t_late_abort, pabort=legacy_pabort, nommu=1 |
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.section ".rodata" |
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string cpu_arch_name, "armv4" |
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string cpu_elf_name, "v4" |
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string cpu_arm740_name, "ARM740T" |
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.align |
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.section ".proc.info.init", "a" |
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.type __arm740_proc_info,#object |
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__arm740_proc_info: |
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.long 0x41807400 |
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.long 0xfffffff0 |
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.long 0 |
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.long 0 |
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initfn __arm740_setup, __arm740_proc_info |
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.long cpu_arch_name |
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.long cpu_elf_name |
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_26BIT |
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.long cpu_arm740_name |
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.long arm740_processor_functions |
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.long 0 |
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.long 0 |
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.long v4_cache_fns @ cache model |
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.size __arm740_proc_info, . - __arm740_proc_info
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