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205 lines
5.2 KiB
205 lines
5.2 KiB
/* SPDX-License-Identifier: GPL-2.0-or-later */ |
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/* |
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* linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720 |
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* |
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* Copyright (C) 2000 Steve Hill (sjhill@cotw.com) |
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* Rob Scott (rscott@mtrob.fdns.net) |
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* Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. |
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* hacked for non-paged-MM by Hyok S. Choi, 2004. |
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* |
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* These are the low level assembler for performing cache and TLB |
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* functions on the ARM720T. The ARM720T has a writethrough IDC |
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* cache, so we don't need to clean it. |
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* |
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* Changelog: |
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* 05-09-2000 SJH Created by moving 720 specific functions |
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* out of 'proc-arm6,7.S' per RMK discussion |
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* 07-25-2000 SJH Added idle function. |
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* 08-25-2000 DBS Updated for integration of ARM Ltd version. |
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* 04-20-2004 HSC modified for non-paged memory management mode. |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <linux/pgtable.h> |
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#include <asm/assembler.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/hwcap.h> |
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#include <asm/pgtable-hwdef.h> |
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#include <asm/ptrace.h> |
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#include "proc-macros.S" |
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/* |
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* Function: arm720_proc_init (void) |
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* : arm720_proc_fin (void) |
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* |
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* Notes : This processor does not require these |
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*/ |
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ENTRY(cpu_arm720_dcache_clean_area) |
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ENTRY(cpu_arm720_proc_init) |
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ret lr |
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ENTRY(cpu_arm720_proc_fin) |
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mrc p15, 0, r0, c1, c0, 0 |
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bic r0, r0, #0x1000 @ ...i............ |
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bic r0, r0, #0x000e @ ............wca. |
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mcr p15, 0, r0, c1, c0, 0 @ disable caches |
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ret lr |
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/* |
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* Function: arm720_proc_do_idle(void) |
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* Params : r0 = unused |
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* Purpose : put the processor in proper idle mode |
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*/ |
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ENTRY(cpu_arm720_do_idle) |
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ret lr |
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/* |
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* Function: arm720_switch_mm(unsigned long pgd_phys) |
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* Params : pgd_phys Physical address of page table |
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* Purpose : Perform a task switch, saving the old process' state and restoring |
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* the new. |
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*/ |
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ENTRY(cpu_arm720_switch_mm) |
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#ifdef CONFIG_MMU |
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mov r1, #0 |
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mcr p15, 0, r1, c7, c7, 0 @ invalidate cache |
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mcr p15, 0, r0, c2, c0, 0 @ update page table ptr |
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mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) |
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#endif |
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ret lr |
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/* |
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* Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) |
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* Params : r0 = Address to set |
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* : r1 = value to set |
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* Purpose : Set a PTE and flush it out of any WB cache |
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*/ |
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.align 5 |
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ENTRY(cpu_arm720_set_pte_ext) |
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#ifdef CONFIG_MMU |
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armv3_set_pte_ext wc_disable=0 |
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#endif |
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ret lr |
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/* |
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* Function: arm720_reset |
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* Params : r0 = address to jump to |
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* Notes : This sets up everything for a reset |
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*/ |
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.pushsection .idmap.text, "ax" |
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ENTRY(cpu_arm720_reset) |
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mov ip, #0 |
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mcr p15, 0, ip, c7, c7, 0 @ invalidate cache |
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#ifdef CONFIG_MMU |
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mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) |
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#endif |
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mrc p15, 0, ip, c1, c0, 0 @ get ctrl register |
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bic ip, ip, #0x000f @ ............wcam |
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bic ip, ip, #0x2100 @ ..v....s........ |
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register |
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ret r0 |
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ENDPROC(cpu_arm720_reset) |
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.popsection |
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.type __arm710_setup, #function |
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__arm710_setup: |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c7, 0 @ invalidate caches |
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#ifdef CONFIG_MMU |
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mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
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#endif |
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mrc p15, 0, r0, c1, c0 @ get control register |
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ldr r5, arm710_cr1_clear |
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bic r0, r0, r5 |
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ldr r5, arm710_cr1_set |
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orr r0, r0, r5 |
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ret lr @ __ret (head.S) |
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.size __arm710_setup, . - __arm710_setup |
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/* |
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* R |
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* .RVI ZFRS BLDP WCAM |
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* .... 0001 ..11 1101 |
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* |
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*/ |
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.type arm710_cr1_clear, #object |
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.type arm710_cr1_set, #object |
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arm710_cr1_clear: |
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.word 0x0f3f |
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arm710_cr1_set: |
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.word 0x013d |
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.type __arm720_setup, #function |
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__arm720_setup: |
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mov r0, #0 |
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mcr p15, 0, r0, c7, c7, 0 @ invalidate caches |
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#ifdef CONFIG_MMU |
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mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
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#endif |
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adr r5, arm720_crval |
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ldmia r5, {r5, r6} |
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mrc p15, 0, r0, c1, c0 @ get control register |
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bic r0, r0, r5 |
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orr r0, r0, r6 |
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ret lr @ __ret (head.S) |
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.size __arm720_setup, . - __arm720_setup |
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/* |
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* R |
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* .RVI ZFRS BLDP WCAM |
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* ..1. 1001 ..11 1101 |
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* |
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*/ |
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.type arm720_crval, #object |
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arm720_crval: |
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crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130 |
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__INITDATA |
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
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define_processor_functions arm720, dabort=v4t_late_abort, pabort=legacy_pabort |
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.section ".rodata" |
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string cpu_arch_name, "armv4t" |
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string cpu_elf_name, "v4" |
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string cpu_arm710_name, "ARM710T" |
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string cpu_arm720_name, "ARM720T" |
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.align |
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/* |
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* See <asm/procinfo.h> for a definition of this structure. |
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*/ |
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.section ".proc.info.init", "a" |
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.macro arm720_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, cpu_flush:req |
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.type __\name\()_proc_info,#object |
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__\name\()_proc_info: |
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.long \cpu_val |
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.long \cpu_mask |
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.long PMD_TYPE_SECT | \ |
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PMD_SECT_BUFFERABLE | \ |
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PMD_SECT_CACHEABLE | \ |
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PMD_BIT4 | \ |
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PMD_SECT_AP_WRITE | \ |
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PMD_SECT_AP_READ |
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.long PMD_TYPE_SECT | \ |
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PMD_BIT4 | \ |
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PMD_SECT_AP_WRITE | \ |
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PMD_SECT_AP_READ |
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initfn \cpu_flush, __\name\()_proc_info @ cpu_flush |
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.long cpu_arch_name @ arch_name |
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.long cpu_elf_name @ elf_name |
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap |
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.long \cpu_name |
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.long arm720_processor_functions |
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.long v4_tlb_fns |
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.long v4wt_user_fns |
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.long v4_cache_fns |
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.size __\name\()_proc_info, . - __\name\()_proc_info |
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.endm |
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arm720_proc_info arm710, 0x41807100, 0xffffff00, cpu_arm710_name, __arm710_setup |
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arm720_proc_info arm720, 0x41807200, 0xffffff00, cpu_arm720_name, __arm720_setup
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