mirror of https://github.com/Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
1686 lines
45 KiB
1686 lines
45 KiB
// SPDX-License-Identifier: GPL-2.0-only |
|
/* |
|
* linux/arch/arm/mm/mmu.c |
|
* |
|
* Copyright (C) 1995-2005 Russell King |
|
*/ |
|
#include <linux/module.h> |
|
#include <linux/kernel.h> |
|
#include <linux/errno.h> |
|
#include <linux/init.h> |
|
#include <linux/mman.h> |
|
#include <linux/nodemask.h> |
|
#include <linux/memblock.h> |
|
#include <linux/fs.h> |
|
#include <linux/vmalloc.h> |
|
#include <linux/sizes.h> |
|
|
|
#include <asm/cp15.h> |
|
#include <asm/cputype.h> |
|
#include <asm/cachetype.h> |
|
#include <asm/sections.h> |
|
#include <asm/setup.h> |
|
#include <asm/smp_plat.h> |
|
#include <asm/tlb.h> |
|
#include <asm/highmem.h> |
|
#include <asm/system_info.h> |
|
#include <asm/traps.h> |
|
#include <asm/procinfo.h> |
|
#include <asm/memory.h> |
|
#include <asm/pgalloc.h> |
|
#include <asm/kasan_def.h> |
|
|
|
#include <asm/mach/arch.h> |
|
#include <asm/mach/map.h> |
|
#include <asm/mach/pci.h> |
|
#include <asm/fixmap.h> |
|
|
|
#include "fault.h" |
|
#include "mm.h" |
|
#include "tcm.h" |
|
|
|
extern unsigned long __atags_pointer; |
|
|
|
/* |
|
* empty_zero_page is a special page that is used for |
|
* zero-initialized data and COW. |
|
*/ |
|
struct page *empty_zero_page; |
|
EXPORT_SYMBOL(empty_zero_page); |
|
|
|
/* |
|
* The pmd table for the upper-most set of pages. |
|
*/ |
|
pmd_t *top_pmd; |
|
|
|
pmdval_t user_pmd_table = _PAGE_USER_TABLE; |
|
|
|
#define CPOLICY_UNCACHED 0 |
|
#define CPOLICY_BUFFERED 1 |
|
#define CPOLICY_WRITETHROUGH 2 |
|
#define CPOLICY_WRITEBACK 3 |
|
#define CPOLICY_WRITEALLOC 4 |
|
|
|
static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; |
|
static unsigned int ecc_mask __initdata = 0; |
|
pgprot_t pgprot_user; |
|
pgprot_t pgprot_kernel; |
|
|
|
EXPORT_SYMBOL(pgprot_user); |
|
EXPORT_SYMBOL(pgprot_kernel); |
|
|
|
struct cachepolicy { |
|
const char policy[16]; |
|
unsigned int cr_mask; |
|
pmdval_t pmd; |
|
pteval_t pte; |
|
}; |
|
|
|
static struct cachepolicy cache_policies[] __initdata = { |
|
{ |
|
.policy = "uncached", |
|
.cr_mask = CR_W|CR_C, |
|
.pmd = PMD_SECT_UNCACHED, |
|
.pte = L_PTE_MT_UNCACHED, |
|
}, { |
|
.policy = "buffered", |
|
.cr_mask = CR_C, |
|
.pmd = PMD_SECT_BUFFERED, |
|
.pte = L_PTE_MT_BUFFERABLE, |
|
}, { |
|
.policy = "writethrough", |
|
.cr_mask = 0, |
|
.pmd = PMD_SECT_WT, |
|
.pte = L_PTE_MT_WRITETHROUGH, |
|
}, { |
|
.policy = "writeback", |
|
.cr_mask = 0, |
|
.pmd = PMD_SECT_WB, |
|
.pte = L_PTE_MT_WRITEBACK, |
|
}, { |
|
.policy = "writealloc", |
|
.cr_mask = 0, |
|
.pmd = PMD_SECT_WBWA, |
|
.pte = L_PTE_MT_WRITEALLOC, |
|
} |
|
}; |
|
|
|
#ifdef CONFIG_CPU_CP15 |
|
static unsigned long initial_pmd_value __initdata = 0; |
|
|
|
/* |
|
* Initialise the cache_policy variable with the initial state specified |
|
* via the "pmd" value. This is used to ensure that on ARMv6 and later, |
|
* the C code sets the page tables up with the same policy as the head |
|
* assembly code, which avoids an illegal state where the TLBs can get |
|
* confused. See comments in early_cachepolicy() for more information. |
|
*/ |
|
void __init init_default_cache_policy(unsigned long pmd) |
|
{ |
|
int i; |
|
|
|
initial_pmd_value = pmd; |
|
|
|
pmd &= PMD_SECT_CACHE_MASK; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cache_policies); i++) |
|
if (cache_policies[i].pmd == pmd) { |
|
cachepolicy = i; |
|
break; |
|
} |
|
|
|
if (i == ARRAY_SIZE(cache_policies)) |
|
pr_err("ERROR: could not find cache policy\n"); |
|
} |
|
|
|
/* |
|
* These are useful for identifying cache coherency problems by allowing |
|
* the cache or the cache and writebuffer to be turned off. (Note: the |
|
* write buffer should not be on and the cache off). |
|
*/ |
|
static int __init early_cachepolicy(char *p) |
|
{ |
|
int i, selected = -1; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { |
|
int len = strlen(cache_policies[i].policy); |
|
|
|
if (memcmp(p, cache_policies[i].policy, len) == 0) { |
|
selected = i; |
|
break; |
|
} |
|
} |
|
|
|
if (selected == -1) |
|
pr_err("ERROR: unknown or unsupported cache policy\n"); |
|
|
|
/* |
|
* This restriction is partly to do with the way we boot; it is |
|
* unpredictable to have memory mapped using two different sets of |
|
* memory attributes (shared, type, and cache attribs). We can not |
|
* change these attributes once the initial assembly has setup the |
|
* page tables. |
|
*/ |
|
if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) { |
|
pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n", |
|
cache_policies[cachepolicy].policy); |
|
return 0; |
|
} |
|
|
|
if (selected != cachepolicy) { |
|
unsigned long cr = __clear_cr(cache_policies[selected].cr_mask); |
|
cachepolicy = selected; |
|
flush_cache_all(); |
|
set_cr(cr); |
|
} |
|
return 0; |
|
} |
|
early_param("cachepolicy", early_cachepolicy); |
|
|
|
static int __init early_nocache(char *__unused) |
|
{ |
|
char *p = "buffered"; |
|
pr_warn("nocache is deprecated; use cachepolicy=%s\n", p); |
|
early_cachepolicy(p); |
|
return 0; |
|
} |
|
early_param("nocache", early_nocache); |
|
|
|
static int __init early_nowrite(char *__unused) |
|
{ |
|
char *p = "uncached"; |
|
pr_warn("nowb is deprecated; use cachepolicy=%s\n", p); |
|
early_cachepolicy(p); |
|
return 0; |
|
} |
|
early_param("nowb", early_nowrite); |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
static int __init early_ecc(char *p) |
|
{ |
|
if (memcmp(p, "on", 2) == 0) |
|
ecc_mask = PMD_PROTECTION; |
|
else if (memcmp(p, "off", 3) == 0) |
|
ecc_mask = 0; |
|
return 0; |
|
} |
|
early_param("ecc", early_ecc); |
|
#endif |
|
|
|
#else /* ifdef CONFIG_CPU_CP15 */ |
|
|
|
static int __init early_cachepolicy(char *p) |
|
{ |
|
pr_warn("cachepolicy kernel parameter not supported without cp15\n"); |
|
} |
|
early_param("cachepolicy", early_cachepolicy); |
|
|
|
static int __init noalign_setup(char *__unused) |
|
{ |
|
pr_warn("noalign kernel parameter not supported without cp15\n"); |
|
} |
|
__setup("noalign", noalign_setup); |
|
|
|
#endif /* ifdef CONFIG_CPU_CP15 / else */ |
|
|
|
#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
|
#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE |
|
#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
|
|
|
static struct mem_type mem_types[] __ro_after_init = { |
|
[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
|
L_PTE_SHARED, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
|
.domain = DOMAIN_IO, |
|
}, |
|
[MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ |
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PROT_SECT_DEVICE, |
|
.domain = DOMAIN_IO, |
|
}, |
|
[MT_DEVICE_CACHED] = { /* ioremap_cache */ |
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, |
|
.domain = DOMAIN_IO, |
|
}, |
|
[MT_DEVICE_WC] = { /* ioremap_wc */ |
|
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PROT_SECT_DEVICE, |
|
.domain = DOMAIN_IO, |
|
}, |
|
[MT_UNCACHED] = { |
|
.prot_pte = PROT_PTE_DEVICE, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
|
.domain = DOMAIN_IO, |
|
}, |
|
[MT_CACHECLEAN] = { |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
#ifndef CONFIG_ARM_LPAE |
|
[MT_MINICLEAN] = { |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
#endif |
|
[MT_LOW_VECTORS] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_RDONLY, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.domain = DOMAIN_VECTORS, |
|
}, |
|
[MT_HIGH_VECTORS] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_USER | L_PTE_RDONLY, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.domain = DOMAIN_VECTORS, |
|
}, |
|
[MT_MEMORY_RWX] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_RW] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_XN, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_ROM] = { |
|
.prot_sect = PMD_TYPE_SECT, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_RWX_NONCACHED] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_MT_BUFFERABLE, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_RW_DTCM] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_XN, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_RWX_ITCM] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_RW_SO] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_MT_UNCACHED | L_PTE_XN, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | |
|
PMD_SECT_UNCACHED | PMD_SECT_XN, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
[MT_MEMORY_DMA_READY] = { |
|
.prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
|
L_PTE_XN, |
|
.prot_l1 = PMD_TYPE_TABLE, |
|
.domain = DOMAIN_KERNEL, |
|
}, |
|
}; |
|
|
|
const struct mem_type *get_mem_type(unsigned int type) |
|
{ |
|
return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; |
|
} |
|
EXPORT_SYMBOL(get_mem_type); |
|
|
|
static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr); |
|
|
|
static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS] |
|
__aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata; |
|
|
|
static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr) |
|
{ |
|
return &bm_pte[pte_index(addr)]; |
|
} |
|
|
|
static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr) |
|
{ |
|
return pte_offset_kernel(dir, addr); |
|
} |
|
|
|
static inline pmd_t * __init fixmap_pmd(unsigned long addr) |
|
{ |
|
return pmd_off_k(addr); |
|
} |
|
|
|
void __init early_fixmap_init(void) |
|
{ |
|
pmd_t *pmd; |
|
|
|
/* |
|
* The early fixmap range spans multiple pmds, for which |
|
* we are not prepared: |
|
*/ |
|
BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT) |
|
!= FIXADDR_TOP >> PMD_SHIFT); |
|
|
|
pmd = fixmap_pmd(FIXADDR_TOP); |
|
pmd_populate_kernel(&init_mm, pmd, bm_pte); |
|
|
|
pte_offset_fixmap = pte_offset_early_fixmap; |
|
} |
|
|
|
/* |
|
* To avoid TLB flush broadcasts, this uses local_flush_tlb_kernel_range(). |
|
* As a result, this can only be called with preemption disabled, as under |
|
* stop_machine(). |
|
*/ |
|
void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot) |
|
{ |
|
unsigned long vaddr = __fix_to_virt(idx); |
|
pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr); |
|
|
|
/* Make sure fixmap region does not exceed available allocation. */ |
|
BUILD_BUG_ON(__fix_to_virt(__end_of_fixed_addresses) < FIXADDR_START); |
|
BUG_ON(idx >= __end_of_fixed_addresses); |
|
|
|
/* we only support device mappings until pgprot_kernel has been set */ |
|
if (WARN_ON(pgprot_val(prot) != pgprot_val(FIXMAP_PAGE_IO) && |
|
pgprot_val(pgprot_kernel) == 0)) |
|
return; |
|
|
|
if (pgprot_val(prot)) |
|
set_pte_at(NULL, vaddr, pte, |
|
pfn_pte(phys >> PAGE_SHIFT, prot)); |
|
else |
|
pte_clear(NULL, vaddr, pte); |
|
local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE); |
|
} |
|
|
|
/* |
|
* Adjust the PMD section entries according to the CPU in use. |
|
*/ |
|
static void __init build_mem_type_table(void) |
|
{ |
|
struct cachepolicy *cp; |
|
unsigned int cr = get_cr(); |
|
pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
|
int cpu_arch = cpu_architecture(); |
|
int i; |
|
|
|
if (cpu_arch < CPU_ARCH_ARMv6) { |
|
#if defined(CONFIG_CPU_DCACHE_DISABLE) |
|
if (cachepolicy > CPOLICY_BUFFERED) |
|
cachepolicy = CPOLICY_BUFFERED; |
|
#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
|
if (cachepolicy > CPOLICY_WRITETHROUGH) |
|
cachepolicy = CPOLICY_WRITETHROUGH; |
|
#endif |
|
} |
|
if (cpu_arch < CPU_ARCH_ARMv5) { |
|
if (cachepolicy >= CPOLICY_WRITEALLOC) |
|
cachepolicy = CPOLICY_WRITEBACK; |
|
ecc_mask = 0; |
|
} |
|
|
|
if (is_smp()) { |
|
if (cachepolicy != CPOLICY_WRITEALLOC) { |
|
pr_warn("Forcing write-allocate cache policy for SMP\n"); |
|
cachepolicy = CPOLICY_WRITEALLOC; |
|
} |
|
if (!(initial_pmd_value & PMD_SECT_S)) { |
|
pr_warn("Forcing shared mappings for SMP\n"); |
|
initial_pmd_value |= PMD_SECT_S; |
|
} |
|
} |
|
|
|
/* |
|
* Strip out features not present on earlier architectures. |
|
* Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those |
|
* without extended page tables don't have the 'Shared' bit. |
|
*/ |
|
if (cpu_arch < CPU_ARCH_ARMv5) |
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
|
mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); |
|
if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) |
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) |
|
mem_types[i].prot_sect &= ~PMD_SECT_S; |
|
|
|
/* |
|
* ARMv5 and lower, bit 4 must be set for page tables (was: cache |
|
* "update-able on write" bit on ARM610). However, Xscale and |
|
* Xscale3 require this bit to be cleared. |
|
*/ |
|
if (cpu_is_xscale_family()) { |
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
|
mem_types[i].prot_sect &= ~PMD_BIT4; |
|
mem_types[i].prot_l1 &= ~PMD_BIT4; |
|
} |
|
} else if (cpu_arch < CPU_ARCH_ARMv6) { |
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
|
if (mem_types[i].prot_l1) |
|
mem_types[i].prot_l1 |= PMD_BIT4; |
|
if (mem_types[i].prot_sect) |
|
mem_types[i].prot_sect |= PMD_BIT4; |
|
} |
|
} |
|
|
|
/* |
|
* Mark the device areas according to the CPU/architecture. |
|
*/ |
|
if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { |
|
if (!cpu_is_xsc3()) { |
|
/* |
|
* Mark device regions on ARMv6+ as execute-never |
|
* to prevent speculative instruction fetches. |
|
*/ |
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; |
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; |
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; |
|
|
|
/* Also setup NX memory mapping */ |
|
mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; |
|
} |
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
|
/* |
|
* For ARMv7 with TEX remapping, |
|
* - shared device is SXCB=1100 |
|
* - nonshared device is SXCB=0100 |
|
* - write combine device mem is SXCB=0001 |
|
* (Uncached Normal memory) |
|
*/ |
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); |
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
|
} else if (cpu_is_xsc3()) { |
|
/* |
|
* For Xscale3, |
|
* - shared device is TEXCB=00101 |
|
* - nonshared device is TEXCB=01000 |
|
* - write combine device mem is TEXCB=00100 |
|
* (Inner/Outer Uncacheable in xsc3 parlance) |
|
*/ |
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; |
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
|
} else { |
|
/* |
|
* For ARMv6 and ARMv7 without TEX remapping, |
|
* - shared device is TEXCB=00001 |
|
* - nonshared device is TEXCB=01000 |
|
* - write combine device mem is TEXCB=00100 |
|
* (Uncached Normal in ARMv6 parlance). |
|
*/ |
|
mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; |
|
mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); |
|
} |
|
} else { |
|
/* |
|
* On others, write combining is "Uncached/Buffered" |
|
*/ |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; |
|
} |
|
|
|
/* |
|
* Now deal with the memory-type mappings |
|
*/ |
|
cp = &cache_policies[cachepolicy]; |
|
vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
/* |
|
* We don't use domains on ARMv6 (since this causes problems with |
|
* v6/v7 kernels), so we must use a separate memory type for user |
|
* r/o, kernel r/w to map the vectors page. |
|
*/ |
|
if (cpu_arch == CPU_ARCH_ARMv6) |
|
vecs_pgprot |= L_PTE_MT_VECTORS; |
|
|
|
/* |
|
* Check is it with support for the PXN bit |
|
* in the Short-descriptor translation table format descriptors. |
|
*/ |
|
if (cpu_arch == CPU_ARCH_ARMv7 && |
|
(read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) { |
|
user_pmd_table |= PMD_PXNTABLE; |
|
} |
|
#endif |
|
|
|
/* |
|
* ARMv6 and above have extended page tables. |
|
*/ |
|
if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { |
|
#ifndef CONFIG_ARM_LPAE |
|
/* |
|
* Mark cache clean areas and XIP ROM read only |
|
* from SVC mode and no access from userspace. |
|
*/ |
|
mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
|
mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; |
|
#endif |
|
|
|
/* |
|
* If the initial page tables were created with the S bit |
|
* set, then we need to do the same here for the same |
|
* reasons given in early_cachepolicy(). |
|
*/ |
|
if (initial_pmd_value & PMD_SECT_S) { |
|
user_pgprot |= L_PTE_SHARED; |
|
kern_pgprot |= L_PTE_SHARED; |
|
vecs_pgprot |= L_PTE_SHARED; |
|
mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
|
mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; |
|
mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; |
|
mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; |
|
mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; |
|
mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; |
|
mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; |
|
mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; |
|
mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; |
|
} |
|
} |
|
|
|
/* |
|
* Non-cacheable Normal - intended for memory areas that must |
|
* not cause dirty cache line writebacks when used |
|
*/ |
|
if (cpu_arch >= CPU_ARCH_ARMv6) { |
|
if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { |
|
/* Non-cacheable Normal is XCB = 001 */ |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
|
PMD_SECT_BUFFERED; |
|
} else { |
|
/* For both ARMv6 and non-TEX-remapping ARMv7 */ |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
|
PMD_SECT_TEX(1); |
|
} |
|
} else { |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
|
} |
|
|
|
#ifdef CONFIG_ARM_LPAE |
|
/* |
|
* Do not generate access flag faults for the kernel mappings. |
|
*/ |
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
|
mem_types[i].prot_pte |= PTE_EXT_AF; |
|
if (mem_types[i].prot_sect) |
|
mem_types[i].prot_sect |= PMD_SECT_AF; |
|
} |
|
kern_pgprot |= PTE_EXT_AF; |
|
vecs_pgprot |= PTE_EXT_AF; |
|
|
|
/* |
|
* Set PXN for user mappings |
|
*/ |
|
user_pgprot |= PTE_EXT_PXN; |
|
#endif |
|
|
|
for (i = 0; i < 16; i++) { |
|
pteval_t v = pgprot_val(protection_map[i]); |
|
protection_map[i] = __pgprot(v | user_pgprot); |
|
} |
|
|
|
mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
|
mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; |
|
|
|
pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
|
pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
|
L_PTE_DIRTY | kern_pgprot); |
|
|
|
mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; |
|
mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; |
|
mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; |
|
mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; |
|
mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; |
|
mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; |
|
mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
|
mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; |
|
mem_types[MT_ROM].prot_sect |= cp->pmd; |
|
|
|
switch (cp->pmd) { |
|
case PMD_SECT_WT: |
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; |
|
break; |
|
case PMD_SECT_WB: |
|
case PMD_SECT_WBWA: |
|
mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; |
|
break; |
|
} |
|
pr_info("Memory policy: %sData cache %s\n", |
|
ecc_mask ? "ECC enabled, " : "", cp->policy); |
|
|
|
for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
|
struct mem_type *t = &mem_types[i]; |
|
if (t->prot_l1) |
|
t->prot_l1 |= PMD_DOMAIN(t->domain); |
|
if (t->prot_sect) |
|
t->prot_sect |= PMD_DOMAIN(t->domain); |
|
} |
|
} |
|
|
|
#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
|
pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, |
|
unsigned long size, pgprot_t vma_prot) |
|
{ |
|
if (!pfn_valid(pfn)) |
|
return pgprot_noncached(vma_prot); |
|
else if (file->f_flags & O_SYNC) |
|
return pgprot_writecombine(vma_prot); |
|
return vma_prot; |
|
} |
|
EXPORT_SYMBOL(phys_mem_access_prot); |
|
#endif |
|
|
|
#define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
|
|
|
static void __init *early_alloc(unsigned long sz) |
|
{ |
|
void *ptr = memblock_alloc(sz, sz); |
|
|
|
if (!ptr) |
|
panic("%s: Failed to allocate %lu bytes align=0x%lx\n", |
|
__func__, sz, sz); |
|
|
|
return ptr; |
|
} |
|
|
|
static void *__init late_alloc(unsigned long sz) |
|
{ |
|
void *ptr = (void *)__get_free_pages(GFP_PGTABLE_KERNEL, get_order(sz)); |
|
|
|
if (!ptr || !pgtable_pte_page_ctor(virt_to_page(ptr))) |
|
BUG(); |
|
return ptr; |
|
} |
|
|
|
static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr, |
|
unsigned long prot, |
|
void *(*alloc)(unsigned long sz)) |
|
{ |
|
if (pmd_none(*pmd)) { |
|
pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
|
__pmd_populate(pmd, __pa(pte), prot); |
|
} |
|
BUG_ON(pmd_bad(*pmd)); |
|
return pte_offset_kernel(pmd, addr); |
|
} |
|
|
|
static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, |
|
unsigned long prot) |
|
{ |
|
return arm_pte_alloc(pmd, addr, prot, early_alloc); |
|
} |
|
|
|
static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
|
unsigned long end, unsigned long pfn, |
|
const struct mem_type *type, |
|
void *(*alloc)(unsigned long sz), |
|
bool ng) |
|
{ |
|
pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc); |
|
do { |
|
set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), |
|
ng ? PTE_EXT_NG : 0); |
|
pfn++; |
|
} while (pte++, addr += PAGE_SIZE, addr != end); |
|
} |
|
|
|
static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
|
unsigned long end, phys_addr_t phys, |
|
const struct mem_type *type, bool ng) |
|
{ |
|
pmd_t *p = pmd; |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
/* |
|
* In classic MMU format, puds and pmds are folded in to |
|
* the pgds. pmd_offset gives the PGD entry. PGDs refer to a |
|
* group of L1 entries making up one logical pointer to |
|
* an L2 table (2MB), where as PMDs refer to the individual |
|
* L1 entries (1MB). Hence increment to get the correct |
|
* offset for odd 1MB sections. |
|
* (See arch/arm/include/asm/pgtable-2level.h) |
|
*/ |
|
if (addr & SECTION_SIZE) |
|
pmd++; |
|
#endif |
|
do { |
|
*pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0)); |
|
phys += SECTION_SIZE; |
|
} while (pmd++, addr += SECTION_SIZE, addr != end); |
|
|
|
flush_pmd_entry(p); |
|
} |
|
|
|
static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
|
unsigned long end, phys_addr_t phys, |
|
const struct mem_type *type, |
|
void *(*alloc)(unsigned long sz), bool ng) |
|
{ |
|
pmd_t *pmd = pmd_offset(pud, addr); |
|
unsigned long next; |
|
|
|
do { |
|
/* |
|
* With LPAE, we must loop over to map |
|
* all the pmds for the given range. |
|
*/ |
|
next = pmd_addr_end(addr, end); |
|
|
|
/* |
|
* Try a section mapping - addr, next and phys must all be |
|
* aligned to a section boundary. |
|
*/ |
|
if (type->prot_sect && |
|
((addr | next | phys) & ~SECTION_MASK) == 0) { |
|
__map_init_section(pmd, addr, next, phys, type, ng); |
|
} else { |
|
alloc_init_pte(pmd, addr, next, |
|
__phys_to_pfn(phys), type, alloc, ng); |
|
} |
|
|
|
phys += next - addr; |
|
|
|
} while (pmd++, addr = next, addr != end); |
|
} |
|
|
|
static void __init alloc_init_pud(p4d_t *p4d, unsigned long addr, |
|
unsigned long end, phys_addr_t phys, |
|
const struct mem_type *type, |
|
void *(*alloc)(unsigned long sz), bool ng) |
|
{ |
|
pud_t *pud = pud_offset(p4d, addr); |
|
unsigned long next; |
|
|
|
do { |
|
next = pud_addr_end(addr, end); |
|
alloc_init_pmd(pud, addr, next, phys, type, alloc, ng); |
|
phys += next - addr; |
|
} while (pud++, addr = next, addr != end); |
|
} |
|
|
|
static void __init alloc_init_p4d(pgd_t *pgd, unsigned long addr, |
|
unsigned long end, phys_addr_t phys, |
|
const struct mem_type *type, |
|
void *(*alloc)(unsigned long sz), bool ng) |
|
{ |
|
p4d_t *p4d = p4d_offset(pgd, addr); |
|
unsigned long next; |
|
|
|
do { |
|
next = p4d_addr_end(addr, end); |
|
alloc_init_pud(p4d, addr, next, phys, type, alloc, ng); |
|
phys += next - addr; |
|
} while (p4d++, addr = next, addr != end); |
|
} |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
static void __init create_36bit_mapping(struct mm_struct *mm, |
|
struct map_desc *md, |
|
const struct mem_type *type, |
|
bool ng) |
|
{ |
|
unsigned long addr, length, end; |
|
phys_addr_t phys; |
|
pgd_t *pgd; |
|
|
|
addr = md->virtual; |
|
phys = __pfn_to_phys(md->pfn); |
|
length = PAGE_ALIGN(md->length); |
|
|
|
if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { |
|
pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n", |
|
(long long)__pfn_to_phys((u64)md->pfn), addr); |
|
return; |
|
} |
|
|
|
/* N.B. ARMv6 supersections are only defined to work with domain 0. |
|
* Since domain assignments can in fact be arbitrary, the |
|
* 'domain == 0' check below is required to insure that ARMv6 |
|
* supersections are only allocated for domain 0 regardless |
|
* of the actual domain assignments in use. |
|
*/ |
|
if (type->domain) { |
|
pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n", |
|
(long long)__pfn_to_phys((u64)md->pfn), addr); |
|
return; |
|
} |
|
|
|
if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { |
|
pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n", |
|
(long long)__pfn_to_phys((u64)md->pfn), addr); |
|
return; |
|
} |
|
|
|
/* |
|
* Shift bits [35:32] of address into bits [23:20] of PMD |
|
* (See ARMv6 spec). |
|
*/ |
|
phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); |
|
|
|
pgd = pgd_offset(mm, addr); |
|
end = addr + length; |
|
do { |
|
p4d_t *p4d = p4d_offset(pgd, addr); |
|
pud_t *pud = pud_offset(p4d, addr); |
|
pmd_t *pmd = pmd_offset(pud, addr); |
|
int i; |
|
|
|
for (i = 0; i < 16; i++) |
|
*pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER | |
|
(ng ? PMD_SECT_nG : 0)); |
|
|
|
addr += SUPERSECTION_SIZE; |
|
phys += SUPERSECTION_SIZE; |
|
pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; |
|
} while (addr != end); |
|
} |
|
#endif /* !CONFIG_ARM_LPAE */ |
|
|
|
static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md, |
|
void *(*alloc)(unsigned long sz), |
|
bool ng) |
|
{ |
|
unsigned long addr, length, end; |
|
phys_addr_t phys; |
|
const struct mem_type *type; |
|
pgd_t *pgd; |
|
|
|
type = &mem_types[md->type]; |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
/* |
|
* Catch 36-bit addresses |
|
*/ |
|
if (md->pfn >= 0x100000) { |
|
create_36bit_mapping(mm, md, type, ng); |
|
return; |
|
} |
|
#endif |
|
|
|
addr = md->virtual & PAGE_MASK; |
|
phys = __pfn_to_phys(md->pfn); |
|
length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
|
|
|
if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
|
pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n", |
|
(long long)__pfn_to_phys(md->pfn), addr); |
|
return; |
|
} |
|
|
|
pgd = pgd_offset(mm, addr); |
|
end = addr + length; |
|
do { |
|
unsigned long next = pgd_addr_end(addr, end); |
|
|
|
alloc_init_p4d(pgd, addr, next, phys, type, alloc, ng); |
|
|
|
phys += next - addr; |
|
addr = next; |
|
} while (pgd++, addr != end); |
|
} |
|
|
|
/* |
|
* Create the page directory entries and any necessary |
|
* page tables for the mapping specified by `md'. We |
|
* are able to cope here with varying sizes and address |
|
* offsets, and we take full advantage of sections and |
|
* supersections. |
|
*/ |
|
static void __init create_mapping(struct map_desc *md) |
|
{ |
|
if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { |
|
pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n", |
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
|
return; |
|
} |
|
|
|
if (md->type == MT_DEVICE && |
|
md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START && |
|
(md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { |
|
pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n", |
|
(long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
|
} |
|
|
|
__create_mapping(&init_mm, md, early_alloc, false); |
|
} |
|
|
|
void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md, |
|
bool ng) |
|
{ |
|
#ifdef CONFIG_ARM_LPAE |
|
p4d_t *p4d; |
|
pud_t *pud; |
|
|
|
p4d = p4d_alloc(mm, pgd_offset(mm, md->virtual), md->virtual); |
|
if (WARN_ON(!p4d)) |
|
return; |
|
pud = pud_alloc(mm, p4d, md->virtual); |
|
if (WARN_ON(!pud)) |
|
return; |
|
pmd_alloc(mm, pud, 0); |
|
#endif |
|
__create_mapping(mm, md, late_alloc, ng); |
|
} |
|
|
|
/* |
|
* Create the architecture specific mappings |
|
*/ |
|
void __init iotable_init(struct map_desc *io_desc, int nr) |
|
{ |
|
struct map_desc *md; |
|
struct vm_struct *vm; |
|
struct static_vm *svm; |
|
|
|
if (!nr) |
|
return; |
|
|
|
svm = memblock_alloc(sizeof(*svm) * nr, __alignof__(*svm)); |
|
if (!svm) |
|
panic("%s: Failed to allocate %zu bytes align=0x%zx\n", |
|
__func__, sizeof(*svm) * nr, __alignof__(*svm)); |
|
|
|
for (md = io_desc; nr; md++, nr--) { |
|
create_mapping(md); |
|
|
|
vm = &svm->vm; |
|
vm->addr = (void *)(md->virtual & PAGE_MASK); |
|
vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
|
vm->phys_addr = __pfn_to_phys(md->pfn); |
|
vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; |
|
vm->flags |= VM_ARM_MTYPE(md->type); |
|
vm->caller = iotable_init; |
|
add_static_vm_early(svm++); |
|
} |
|
} |
|
|
|
void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
|
void *caller) |
|
{ |
|
struct vm_struct *vm; |
|
struct static_vm *svm; |
|
|
|
svm = memblock_alloc(sizeof(*svm), __alignof__(*svm)); |
|
if (!svm) |
|
panic("%s: Failed to allocate %zu bytes align=0x%zx\n", |
|
__func__, sizeof(*svm), __alignof__(*svm)); |
|
|
|
vm = &svm->vm; |
|
vm->addr = (void *)addr; |
|
vm->size = size; |
|
vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
|
vm->caller = caller; |
|
add_static_vm_early(svm); |
|
} |
|
|
|
#ifndef CONFIG_ARM_LPAE |
|
|
|
/* |
|
* The Linux PMD is made of two consecutive section entries covering 2MB |
|
* (see definition in include/asm/pgtable-2level.h). However a call to |
|
* create_mapping() may optimize static mappings by using individual |
|
* 1MB section mappings. This leaves the actual PMD potentially half |
|
* initialized if the top or bottom section entry isn't used, leaving it |
|
* open to problems if a subsequent ioremap() or vmalloc() tries to use |
|
* the virtual space left free by that unused section entry. |
|
* |
|
* Let's avoid the issue by inserting dummy vm entries covering the unused |
|
* PMD halves once the static mappings are in place. |
|
*/ |
|
|
|
static void __init pmd_empty_section_gap(unsigned long addr) |
|
{ |
|
vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
|
} |
|
|
|
static void __init fill_pmd_gaps(void) |
|
{ |
|
struct static_vm *svm; |
|
struct vm_struct *vm; |
|
unsigned long addr, next = 0; |
|
pmd_t *pmd; |
|
|
|
list_for_each_entry(svm, &static_vmlist, list) { |
|
vm = &svm->vm; |
|
addr = (unsigned long)vm->addr; |
|
if (addr < next) |
|
continue; |
|
|
|
/* |
|
* Check if this vm starts on an odd section boundary. |
|
* If so and the first section entry for this PMD is free |
|
* then we block the corresponding virtual address. |
|
*/ |
|
if ((addr & ~PMD_MASK) == SECTION_SIZE) { |
|
pmd = pmd_off_k(addr); |
|
if (pmd_none(*pmd)) |
|
pmd_empty_section_gap(addr & PMD_MASK); |
|
} |
|
|
|
/* |
|
* Then check if this vm ends on an odd section boundary. |
|
* If so and the second section entry for this PMD is empty |
|
* then we block the corresponding virtual address. |
|
*/ |
|
addr += vm->size; |
|
if ((addr & ~PMD_MASK) == SECTION_SIZE) { |
|
pmd = pmd_off_k(addr) + 1; |
|
if (pmd_none(*pmd)) |
|
pmd_empty_section_gap(addr); |
|
} |
|
|
|
/* no need to look at any vm entry until we hit the next PMD */ |
|
next = (addr + PMD_SIZE - 1) & PMD_MASK; |
|
} |
|
} |
|
|
|
#else |
|
#define fill_pmd_gaps() do { } while (0) |
|
#endif |
|
|
|
#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
|
static void __init pci_reserve_io(void) |
|
{ |
|
struct static_vm *svm; |
|
|
|
svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
|
if (svm) |
|
return; |
|
|
|
vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
|
} |
|
#else |
|
#define pci_reserve_io() do { } while (0) |
|
#endif |
|
|
|
#ifdef CONFIG_DEBUG_LL |
|
void __init debug_ll_io_init(void) |
|
{ |
|
struct map_desc map; |
|
|
|
debug_ll_addr(&map.pfn, &map.virtual); |
|
if (!map.pfn || !map.virtual) |
|
return; |
|
map.pfn = __phys_to_pfn(map.pfn); |
|
map.virtual &= PAGE_MASK; |
|
map.length = PAGE_SIZE; |
|
map.type = MT_DEVICE; |
|
iotable_init(&map, 1); |
|
} |
|
#endif |
|
|
|
static void * __initdata vmalloc_min = |
|
(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); |
|
|
|
/* |
|
* vmalloc=size forces the vmalloc area to be exactly 'size' |
|
* bytes. This can be used to increase (or decrease) the vmalloc |
|
* area - the default is 240m. |
|
*/ |
|
static int __init early_vmalloc(char *arg) |
|
{ |
|
unsigned long vmalloc_reserve = memparse(arg, NULL); |
|
|
|
if (vmalloc_reserve < SZ_16M) { |
|
vmalloc_reserve = SZ_16M; |
|
pr_warn("vmalloc area too small, limiting to %luMB\n", |
|
vmalloc_reserve >> 20); |
|
} |
|
|
|
if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { |
|
vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); |
|
pr_warn("vmalloc area is too big, limiting to %luMB\n", |
|
vmalloc_reserve >> 20); |
|
} |
|
|
|
vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); |
|
return 0; |
|
} |
|
early_param("vmalloc", early_vmalloc); |
|
|
|
phys_addr_t arm_lowmem_limit __initdata = 0; |
|
|
|
void __init adjust_lowmem_bounds(void) |
|
{ |
|
phys_addr_t block_start, block_end, memblock_limit = 0; |
|
u64 vmalloc_limit, i; |
|
phys_addr_t lowmem_limit = 0; |
|
|
|
/* |
|
* Let's use our own (unoptimized) equivalent of __pa() that is |
|
* not affected by wrap-arounds when sizeof(phys_addr_t) == 4. |
|
* The result is used as the upper bound on physical memory address |
|
* and may itself be outside the valid range for which phys_addr_t |
|
* and therefore __pa() is defined. |
|
*/ |
|
vmalloc_limit = (u64)(uintptr_t)vmalloc_min - PAGE_OFFSET + PHYS_OFFSET; |
|
|
|
/* |
|
* The first usable region must be PMD aligned. Mark its start |
|
* as MEMBLOCK_NOMAP if it isn't |
|
*/ |
|
for_each_mem_range(i, &block_start, &block_end) { |
|
if (!IS_ALIGNED(block_start, PMD_SIZE)) { |
|
phys_addr_t len; |
|
|
|
len = round_up(block_start, PMD_SIZE) - block_start; |
|
memblock_mark_nomap(block_start, len); |
|
} |
|
break; |
|
} |
|
|
|
for_each_mem_range(i, &block_start, &block_end) { |
|
if (block_start < vmalloc_limit) { |
|
if (block_end > lowmem_limit) |
|
/* |
|
* Compare as u64 to ensure vmalloc_limit does |
|
* not get truncated. block_end should always |
|
* fit in phys_addr_t so there should be no |
|
* issue with assignment. |
|
*/ |
|
lowmem_limit = min_t(u64, |
|
vmalloc_limit, |
|
block_end); |
|
|
|
/* |
|
* Find the first non-pmd-aligned page, and point |
|
* memblock_limit at it. This relies on rounding the |
|
* limit down to be pmd-aligned, which happens at the |
|
* end of this function. |
|
* |
|
* With this algorithm, the start or end of almost any |
|
* bank can be non-pmd-aligned. The only exception is |
|
* that the start of the bank 0 must be section- |
|
* aligned, since otherwise memory would need to be |
|
* allocated when mapping the start of bank 0, which |
|
* occurs before any free memory is mapped. |
|
*/ |
|
if (!memblock_limit) { |
|
if (!IS_ALIGNED(block_start, PMD_SIZE)) |
|
memblock_limit = block_start; |
|
else if (!IS_ALIGNED(block_end, PMD_SIZE)) |
|
memblock_limit = lowmem_limit; |
|
} |
|
|
|
} |
|
} |
|
|
|
arm_lowmem_limit = lowmem_limit; |
|
|
|
high_memory = __va(arm_lowmem_limit - 1) + 1; |
|
|
|
if (!memblock_limit) |
|
memblock_limit = arm_lowmem_limit; |
|
|
|
/* |
|
* Round the memblock limit down to a pmd size. This |
|
* helps to ensure that we will allocate memory from the |
|
* last full pmd, which should be mapped. |
|
*/ |
|
memblock_limit = round_down(memblock_limit, PMD_SIZE); |
|
|
|
if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) { |
|
if (memblock_end_of_DRAM() > arm_lowmem_limit) { |
|
phys_addr_t end = memblock_end_of_DRAM(); |
|
|
|
pr_notice("Ignoring RAM at %pa-%pa\n", |
|
&memblock_limit, &end); |
|
pr_notice("Consider using a HIGHMEM enabled kernel.\n"); |
|
|
|
memblock_remove(memblock_limit, end - memblock_limit); |
|
} |
|
} |
|
|
|
memblock_set_current_limit(memblock_limit); |
|
} |
|
|
|
static inline void prepare_page_table(void) |
|
{ |
|
unsigned long addr; |
|
phys_addr_t end; |
|
|
|
/* |
|
* Clear out all the mappings below the kernel image. |
|
*/ |
|
#ifdef CONFIG_KASAN |
|
/* |
|
* KASan's shadow memory inserts itself between the TASK_SIZE |
|
* and MODULES_VADDR. Do not clear the KASan shadow memory mappings. |
|
*/ |
|
for (addr = 0; addr < KASAN_SHADOW_START; addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
/* |
|
* Skip over the KASan shadow area. KASAN_SHADOW_END is sometimes |
|
* equal to MODULES_VADDR and then we exit the pmd clearing. If we |
|
* are using a thumb-compiled kernel, there there will be 8MB more |
|
* to clear as KASan always offset to 16 MB below MODULES_VADDR. |
|
*/ |
|
for (addr = KASAN_SHADOW_END; addr < MODULES_VADDR; addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
#else |
|
for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
#endif |
|
|
|
#ifdef CONFIG_XIP_KERNEL |
|
/* The XIP kernel is mapped in the module area -- skip over it */ |
|
addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK; |
|
#endif |
|
for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
|
|
/* |
|
* Find the end of the first block of lowmem. |
|
*/ |
|
end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; |
|
if (end >= arm_lowmem_limit) |
|
end = arm_lowmem_limit; |
|
|
|
/* |
|
* Clear out all the kernel space mappings, except for the first |
|
* memory bank, up to the vmalloc region. |
|
*/ |
|
for (addr = __phys_to_virt(end); |
|
addr < VMALLOC_START; addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
} |
|
|
|
#ifdef CONFIG_ARM_LPAE |
|
/* the first page is reserved for pgd */ |
|
#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ |
|
PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) |
|
#else |
|
#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
|
#endif |
|
|
|
/* |
|
* Reserve the special regions of memory |
|
*/ |
|
void __init arm_mm_memblock_reserve(void) |
|
{ |
|
/* |
|
* Reserve the page tables. These are already in use, |
|
* and can only be in node 0. |
|
*/ |
|
memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
|
|
|
#ifdef CONFIG_SA1111 |
|
/* |
|
* Because of the SA1111 DMA bug, we want to preserve our |
|
* precious DMA-able memory... |
|
*/ |
|
memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
|
#endif |
|
} |
|
|
|
/* |
|
* Set up the device mappings. Since we clear out the page tables for all |
|
* mappings above VMALLOC_START, except early fixmap, we might remove debug |
|
* device mappings. This means earlycon can be used to debug this function |
|
* Any other function or debugging method which may touch any device _will_ |
|
* crash the kernel. |
|
*/ |
|
static void __init devicemaps_init(const struct machine_desc *mdesc) |
|
{ |
|
struct map_desc map; |
|
unsigned long addr; |
|
void *vectors; |
|
|
|
/* |
|
* Allocate the vector page early. |
|
*/ |
|
vectors = early_alloc(PAGE_SIZE * 2); |
|
|
|
early_trap_init(vectors); |
|
|
|
/* |
|
* Clear page table except top pmd used by early fixmaps |
|
*/ |
|
for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE) |
|
pmd_clear(pmd_off_k(addr)); |
|
|
|
if (__atags_pointer) { |
|
/* create a read-only mapping of the device tree */ |
|
map.pfn = __phys_to_pfn(__atags_pointer & SECTION_MASK); |
|
map.virtual = FDT_FIXED_BASE; |
|
map.length = FDT_FIXED_SIZE; |
|
map.type = MT_ROM; |
|
create_mapping(&map); |
|
} |
|
|
|
/* |
|
* Map the kernel if it is XIP. |
|
* It is always first in the modulearea. |
|
*/ |
|
#ifdef CONFIG_XIP_KERNEL |
|
map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); |
|
map.virtual = MODULES_VADDR; |
|
map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
|
map.type = MT_ROM; |
|
create_mapping(&map); |
|
#endif |
|
|
|
/* |
|
* Map the cache flushing regions. |
|
*/ |
|
#ifdef FLUSH_BASE |
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); |
|
map.virtual = FLUSH_BASE; |
|
map.length = SZ_1M; |
|
map.type = MT_CACHECLEAN; |
|
create_mapping(&map); |
|
#endif |
|
#ifdef FLUSH_BASE_MINICACHE |
|
map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); |
|
map.virtual = FLUSH_BASE_MINICACHE; |
|
map.length = SZ_1M; |
|
map.type = MT_MINICLEAN; |
|
create_mapping(&map); |
|
#endif |
|
|
|
/* |
|
* Create a mapping for the machine vectors at the high-vectors |
|
* location (0xffff0000). If we aren't using high-vectors, also |
|
* create a mapping at the low-vectors virtual address. |
|
*/ |
|
map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
|
map.virtual = 0xffff0000; |
|
map.length = PAGE_SIZE; |
|
#ifdef CONFIG_KUSER_HELPERS |
|
map.type = MT_HIGH_VECTORS; |
|
#else |
|
map.type = MT_LOW_VECTORS; |
|
#endif |
|
create_mapping(&map); |
|
|
|
if (!vectors_high()) { |
|
map.virtual = 0; |
|
map.length = PAGE_SIZE * 2; |
|
map.type = MT_LOW_VECTORS; |
|
create_mapping(&map); |
|
} |
|
|
|
/* Now create a kernel read-only mapping */ |
|
map.pfn += 1; |
|
map.virtual = 0xffff0000 + PAGE_SIZE; |
|
map.length = PAGE_SIZE; |
|
map.type = MT_LOW_VECTORS; |
|
create_mapping(&map); |
|
|
|
/* |
|
* Ask the machine support to map in the statically mapped devices. |
|
*/ |
|
if (mdesc->map_io) |
|
mdesc->map_io(); |
|
else |
|
debug_ll_io_init(); |
|
fill_pmd_gaps(); |
|
|
|
/* Reserve fixed i/o space in VMALLOC region */ |
|
pci_reserve_io(); |
|
|
|
/* |
|
* Finally flush the caches and tlb to ensure that we're in a |
|
* consistent state wrt the writebuffer. This also ensures that |
|
* any write-allocated cache lines in the vector page are written |
|
* back. After this point, we can start to touch devices again. |
|
*/ |
|
local_flush_tlb_all(); |
|
flush_cache_all(); |
|
|
|
/* Enable asynchronous aborts */ |
|
early_abt_enable(); |
|
} |
|
|
|
static void __init kmap_init(void) |
|
{ |
|
#ifdef CONFIG_HIGHMEM |
|
pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
|
PKMAP_BASE, _PAGE_KERNEL_TABLE); |
|
#endif |
|
|
|
early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START, |
|
_PAGE_KERNEL_TABLE); |
|
} |
|
|
|
static void __init map_lowmem(void) |
|
{ |
|
phys_addr_t kernel_x_start = round_down(__pa(KERNEL_START), SECTION_SIZE); |
|
phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); |
|
phys_addr_t start, end; |
|
u64 i; |
|
|
|
/* Map all the lowmem memory banks. */ |
|
for_each_mem_range(i, &start, &end) { |
|
struct map_desc map; |
|
|
|
if (end > arm_lowmem_limit) |
|
end = arm_lowmem_limit; |
|
if (start >= end) |
|
break; |
|
|
|
if (end < kernel_x_start) { |
|
map.pfn = __phys_to_pfn(start); |
|
map.virtual = __phys_to_virt(start); |
|
map.length = end - start; |
|
map.type = MT_MEMORY_RWX; |
|
|
|
create_mapping(&map); |
|
} else if (start >= kernel_x_end) { |
|
map.pfn = __phys_to_pfn(start); |
|
map.virtual = __phys_to_virt(start); |
|
map.length = end - start; |
|
map.type = MT_MEMORY_RW; |
|
|
|
create_mapping(&map); |
|
} else { |
|
/* This better cover the entire kernel */ |
|
if (start < kernel_x_start) { |
|
map.pfn = __phys_to_pfn(start); |
|
map.virtual = __phys_to_virt(start); |
|
map.length = kernel_x_start - start; |
|
map.type = MT_MEMORY_RW; |
|
|
|
create_mapping(&map); |
|
} |
|
|
|
map.pfn = __phys_to_pfn(kernel_x_start); |
|
map.virtual = __phys_to_virt(kernel_x_start); |
|
map.length = kernel_x_end - kernel_x_start; |
|
map.type = MT_MEMORY_RWX; |
|
|
|
create_mapping(&map); |
|
|
|
if (kernel_x_end < end) { |
|
map.pfn = __phys_to_pfn(kernel_x_end); |
|
map.virtual = __phys_to_virt(kernel_x_end); |
|
map.length = end - kernel_x_end; |
|
map.type = MT_MEMORY_RW; |
|
|
|
create_mapping(&map); |
|
} |
|
} |
|
} |
|
} |
|
|
|
#ifdef CONFIG_ARM_PV_FIXUP |
|
typedef void pgtables_remap(long long offset, unsigned long pgd); |
|
pgtables_remap lpae_pgtables_remap_asm; |
|
|
|
/* |
|
* early_paging_init() recreates boot time page table setup, allowing machines |
|
* to switch over to a high (>4G) address space on LPAE systems |
|
*/ |
|
static void __init early_paging_init(const struct machine_desc *mdesc) |
|
{ |
|
pgtables_remap *lpae_pgtables_remap; |
|
unsigned long pa_pgd; |
|
unsigned int cr, ttbcr; |
|
long long offset; |
|
|
|
if (!mdesc->pv_fixup) |
|
return; |
|
|
|
offset = mdesc->pv_fixup(); |
|
if (offset == 0) |
|
return; |
|
|
|
/* |
|
* Get the address of the remap function in the 1:1 identity |
|
* mapping setup by the early page table assembly code. We |
|
* must get this prior to the pv update. The following barrier |
|
* ensures that this is complete before we fixup any P:V offsets. |
|
*/ |
|
lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm); |
|
pa_pgd = __pa(swapper_pg_dir); |
|
barrier(); |
|
|
|
pr_info("Switching physical address space to 0x%08llx\n", |
|
(u64)PHYS_OFFSET + offset); |
|
|
|
/* Re-set the phys pfn offset, and the pv offset */ |
|
__pv_offset += offset; |
|
__pv_phys_pfn_offset += PFN_DOWN(offset); |
|
|
|
/* Run the patch stub to update the constants */ |
|
fixup_pv_table(&__pv_table_begin, |
|
(&__pv_table_end - &__pv_table_begin) << 2); |
|
|
|
/* |
|
* We changing not only the virtual to physical mapping, but also |
|
* the physical addresses used to access memory. We need to flush |
|
* all levels of cache in the system with caching disabled to |
|
* ensure that all data is written back, and nothing is prefetched |
|
* into the caches. We also need to prevent the TLB walkers |
|
* allocating into the caches too. Note that this is ARMv7 LPAE |
|
* specific. |
|
*/ |
|
cr = get_cr(); |
|
set_cr(cr & ~(CR_I | CR_C)); |
|
asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr)); |
|
asm volatile("mcr p15, 0, %0, c2, c0, 2" |
|
: : "r" (ttbcr & ~(3 << 8 | 3 << 10))); |
|
flush_cache_all(); |
|
|
|
/* |
|
* Fixup the page tables - this must be in the idmap region as |
|
* we need to disable the MMU to do this safely, and hence it |
|
* needs to be assembly. It's fairly simple, as we're using the |
|
* temporary tables setup by the initial assembly code. |
|
*/ |
|
lpae_pgtables_remap(offset, pa_pgd); |
|
|
|
/* Re-enable the caches and cacheable TLB walks */ |
|
asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr)); |
|
set_cr(cr); |
|
} |
|
|
|
#else |
|
|
|
static void __init early_paging_init(const struct machine_desc *mdesc) |
|
{ |
|
long long offset; |
|
|
|
if (!mdesc->pv_fixup) |
|
return; |
|
|
|
offset = mdesc->pv_fixup(); |
|
if (offset == 0) |
|
return; |
|
|
|
pr_crit("Physical address space modification is only to support Keystone2.\n"); |
|
pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n"); |
|
pr_crit("feature. Your kernel may crash now, have a good day.\n"); |
|
add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); |
|
} |
|
|
|
#endif |
|
|
|
static void __init early_fixmap_shutdown(void) |
|
{ |
|
int i; |
|
unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1); |
|
|
|
pte_offset_fixmap = pte_offset_late_fixmap; |
|
pmd_clear(fixmap_pmd(va)); |
|
local_flush_tlb_kernel_page(va); |
|
|
|
for (i = 0; i < __end_of_permanent_fixed_addresses; i++) { |
|
pte_t *pte; |
|
struct map_desc map; |
|
|
|
map.virtual = fix_to_virt(i); |
|
pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual); |
|
|
|
/* Only i/o device mappings are supported ATM */ |
|
if (pte_none(*pte) || |
|
(pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED) |
|
continue; |
|
|
|
map.pfn = pte_pfn(*pte); |
|
map.type = MT_DEVICE; |
|
map.length = PAGE_SIZE; |
|
|
|
create_mapping(&map); |
|
} |
|
} |
|
|
|
/* |
|
* paging_init() sets up the page tables, initialises the zone memory |
|
* maps, and sets up the zero page, bad page and bad page tables. |
|
*/ |
|
void __init paging_init(const struct machine_desc *mdesc) |
|
{ |
|
void *zero_page; |
|
|
|
prepare_page_table(); |
|
map_lowmem(); |
|
memblock_set_current_limit(arm_lowmem_limit); |
|
dma_contiguous_remap(); |
|
early_fixmap_shutdown(); |
|
devicemaps_init(mdesc); |
|
kmap_init(); |
|
tcm_init(); |
|
|
|
top_pmd = pmd_off_k(0xffff0000); |
|
|
|
/* allocate the zero page. */ |
|
zero_page = early_alloc(PAGE_SIZE); |
|
|
|
bootmem_init(); |
|
|
|
empty_zero_page = virt_to_page(zero_page); |
|
__flush_dcache_page(NULL, empty_zero_page); |
|
} |
|
|
|
void __init early_mm_init(const struct machine_desc *mdesc) |
|
{ |
|
build_mem_type_table(); |
|
early_paging_init(mdesc); |
|
} |
|
|
|
void set_pte_at(struct mm_struct *mm, unsigned long addr, |
|
pte_t *ptep, pte_t pteval) |
|
{ |
|
unsigned long ext = 0; |
|
|
|
if (addr < TASK_SIZE && pte_valid_user(pteval)) { |
|
if (!pte_special(pteval)) |
|
__sync_icache_dcache(pteval); |
|
ext |= PTE_EXT_NG; |
|
} |
|
|
|
set_pte_ext(ptep, pteval, ext); |
|
}
|
|
|