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392 lines
9.0 KiB
392 lines
9.0 KiB
/* |
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* arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support |
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* |
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* Copyright (C) 2008 Marvell Semiconductor |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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* |
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* References: |
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* - Unified Layer 2 Cache for Feroceon CPU Cores, |
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* Document ID MV-S104858-00, Rev. A, October 23 2007. |
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*/ |
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#include <linux/init.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/highmem.h> |
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#include <linux/io.h> |
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#include <asm/cacheflush.h> |
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#include <asm/cp15.h> |
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#include <asm/hardware/cache-feroceon-l2.h> |
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#define L2_WRITETHROUGH_KIRKWOOD BIT(4) |
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/* |
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* Low-level cache maintenance operations. |
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* |
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* As well as the regular 'clean/invalidate/flush L2 cache line by |
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* MVA' instructions, the Feroceon L2 cache controller also features |
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* 'clean/invalidate L2 range by MVA' operations. |
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* |
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* Cache range operations are initiated by writing the start and |
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* end addresses to successive cp15 registers, and process every |
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* cache line whose first byte address lies in the inclusive range |
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* [start:end]. |
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* |
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* The cache range operations stall the CPU pipeline until completion. |
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* |
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* The range operations require two successive cp15 writes, in |
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* between which we don't want to be preempted. |
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*/ |
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static inline unsigned long l2_get_va(unsigned long paddr) |
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{ |
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#ifdef CONFIG_HIGHMEM |
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/* |
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* Because range ops can't be done on physical addresses, |
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* we simply install a virtual mapping for it only for the |
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* TLB lookup to occur, hence no need to flush the untouched |
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* memory mapping afterwards (note: a cache flush may happen |
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* in some circumstances depending on the path taken in kunmap_atomic). |
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*/ |
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void *vaddr = kmap_atomic_pfn(paddr >> PAGE_SHIFT); |
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return (unsigned long)vaddr + (paddr & ~PAGE_MASK); |
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#else |
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return __phys_to_virt(paddr); |
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#endif |
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} |
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static inline void l2_put_va(unsigned long vaddr) |
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{ |
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#ifdef CONFIG_HIGHMEM |
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kunmap_atomic((void *)vaddr); |
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#endif |
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} |
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static inline void l2_clean_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr)); |
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} |
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static inline void l2_clean_pa_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long va_start, va_end, flags; |
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/* |
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* Make sure 'start' and 'end' reference the same page, as |
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* L2 is PIPT and range operations only do a TLB lookup on |
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* the start address. |
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*/ |
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BUG_ON((start ^ end) >> PAGE_SHIFT); |
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va_start = l2_get_va(start); |
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va_end = va_start + (end - start); |
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raw_local_irq_save(flags); |
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__asm__("mcr p15, 1, %0, c15, c9, 4\n\t" |
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"mcr p15, 1, %1, c15, c9, 5" |
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: : "r" (va_start), "r" (va_end)); |
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raw_local_irq_restore(flags); |
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l2_put_va(va_start); |
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} |
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static inline void l2_clean_inv_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr)); |
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} |
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static inline void l2_inv_pa(unsigned long addr) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr)); |
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} |
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static inline void l2_inv_pa_range(unsigned long start, unsigned long end) |
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{ |
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unsigned long va_start, va_end, flags; |
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/* |
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* Make sure 'start' and 'end' reference the same page, as |
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* L2 is PIPT and range operations only do a TLB lookup on |
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* the start address. |
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*/ |
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BUG_ON((start ^ end) >> PAGE_SHIFT); |
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va_start = l2_get_va(start); |
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va_end = va_start + (end - start); |
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raw_local_irq_save(flags); |
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__asm__("mcr p15, 1, %0, c15, c11, 4\n\t" |
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"mcr p15, 1, %1, c15, c11, 5" |
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: : "r" (va_start), "r" (va_end)); |
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raw_local_irq_restore(flags); |
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l2_put_va(va_start); |
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} |
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static inline void l2_inv_all(void) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c11, 0" : : "r" (0)); |
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} |
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/* |
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* Linux primitives. |
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* |
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* Note that the end addresses passed to Linux primitives are |
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* noninclusive, while the hardware cache range operations use |
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* inclusive start and end addresses. |
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*/ |
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#define CACHE_LINE_SIZE 32 |
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#define MAX_RANGE_SIZE 1024 |
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static int l2_wt_override; |
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static unsigned long calc_range_end(unsigned long start, unsigned long end) |
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{ |
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unsigned long range_end; |
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BUG_ON(start & (CACHE_LINE_SIZE - 1)); |
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BUG_ON(end & (CACHE_LINE_SIZE - 1)); |
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/* |
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* Try to process all cache lines between 'start' and 'end'. |
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*/ |
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range_end = end; |
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/* |
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* Limit the number of cache lines processed at once, |
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* since cache range operations stall the CPU pipeline |
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* until completion. |
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*/ |
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if (range_end > start + MAX_RANGE_SIZE) |
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range_end = start + MAX_RANGE_SIZE; |
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/* |
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* Cache range operations can't straddle a page boundary. |
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*/ |
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if (range_end > (start | (PAGE_SIZE - 1)) + 1) |
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range_end = (start | (PAGE_SIZE - 1)) + 1; |
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return range_end; |
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} |
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static void feroceon_l2_inv_range(unsigned long start, unsigned long end) |
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{ |
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/* |
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* Clean and invalidate partial first cache line. |
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*/ |
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if (start & (CACHE_LINE_SIZE - 1)) { |
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l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); |
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start = (start | (CACHE_LINE_SIZE - 1)) + 1; |
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} |
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/* |
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* Clean and invalidate partial last cache line. |
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*/ |
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if (start < end && end & (CACHE_LINE_SIZE - 1)) { |
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l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); |
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end &= ~(CACHE_LINE_SIZE - 1); |
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} |
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/* |
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* Invalidate all full cache lines between 'start' and 'end'. |
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*/ |
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while (start < end) { |
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unsigned long range_end = calc_range_end(start, end); |
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l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); |
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start = range_end; |
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} |
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dsb(); |
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} |
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static void feroceon_l2_clean_range(unsigned long start, unsigned long end) |
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{ |
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/* |
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* If L2 is forced to WT, the L2 will always be clean and we |
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* don't need to do anything here. |
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*/ |
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if (!l2_wt_override) { |
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start &= ~(CACHE_LINE_SIZE - 1); |
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end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); |
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while (start != end) { |
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unsigned long range_end = calc_range_end(start, end); |
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l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); |
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start = range_end; |
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} |
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} |
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dsb(); |
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} |
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static void feroceon_l2_flush_range(unsigned long start, unsigned long end) |
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{ |
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start &= ~(CACHE_LINE_SIZE - 1); |
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end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); |
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while (start != end) { |
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unsigned long range_end = calc_range_end(start, end); |
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if (!l2_wt_override) |
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l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); |
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l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); |
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start = range_end; |
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} |
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dsb(); |
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} |
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/* |
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* Routines to disable and re-enable the D-cache and I-cache at run |
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* time. These are necessary because the L2 cache can only be enabled |
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* or disabled while the L1 Dcache and Icache are both disabled. |
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*/ |
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static int __init flush_and_disable_dcache(void) |
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{ |
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u32 cr; |
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cr = get_cr(); |
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if (cr & CR_C) { |
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unsigned long flags; |
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raw_local_irq_save(flags); |
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flush_cache_all(); |
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set_cr(cr & ~CR_C); |
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raw_local_irq_restore(flags); |
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return 1; |
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} |
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return 0; |
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} |
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static void __init enable_dcache(void) |
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{ |
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u32 cr; |
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cr = get_cr(); |
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set_cr(cr | CR_C); |
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} |
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static void __init __invalidate_icache(void) |
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{ |
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__asm__("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); |
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} |
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static int __init invalidate_and_disable_icache(void) |
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{ |
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u32 cr; |
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cr = get_cr(); |
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if (cr & CR_I) { |
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set_cr(cr & ~CR_I); |
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__invalidate_icache(); |
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return 1; |
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} |
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return 0; |
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} |
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static void __init enable_icache(void) |
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{ |
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u32 cr; |
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cr = get_cr(); |
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set_cr(cr | CR_I); |
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} |
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static inline u32 read_extra_features(void) |
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{ |
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u32 u; |
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__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u)); |
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return u; |
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} |
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static inline void write_extra_features(u32 u) |
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{ |
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__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u)); |
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} |
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static void __init disable_l2_prefetch(void) |
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{ |
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u32 u; |
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/* |
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* Read the CPU Extra Features register and verify that the |
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* Disable L2 Prefetch bit is set. |
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*/ |
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u = read_extra_features(); |
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if (!(u & 0x01000000)) { |
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pr_info("Feroceon L2: Disabling L2 prefetch.\n"); |
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write_extra_features(u | 0x01000000); |
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} |
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} |
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static void __init enable_l2(void) |
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{ |
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u32 u; |
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u = read_extra_features(); |
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if (!(u & 0x00400000)) { |
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int i, d; |
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pr_info("Feroceon L2: Enabling L2\n"); |
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d = flush_and_disable_dcache(); |
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i = invalidate_and_disable_icache(); |
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l2_inv_all(); |
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write_extra_features(u | 0x00400000); |
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if (i) |
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enable_icache(); |
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if (d) |
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enable_dcache(); |
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} else |
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pr_err(FW_BUG |
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"Feroceon L2: bootloader left the L2 cache on!\n"); |
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} |
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void __init feroceon_l2_init(int __l2_wt_override) |
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{ |
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l2_wt_override = __l2_wt_override; |
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disable_l2_prefetch(); |
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outer_cache.inv_range = feroceon_l2_inv_range; |
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outer_cache.clean_range = feroceon_l2_clean_range; |
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outer_cache.flush_range = feroceon_l2_flush_range; |
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enable_l2(); |
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pr_info("Feroceon L2: Cache support initialised%s.\n", |
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l2_wt_override ? ", in WT override mode" : ""); |
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} |
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#ifdef CONFIG_OF |
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static const struct of_device_id feroceon_ids[] __initconst = { |
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{ .compatible = "marvell,kirkwood-cache"}, |
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{ .compatible = "marvell,feroceon-cache"}, |
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{} |
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}; |
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int __init feroceon_of_init(void) |
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{ |
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struct device_node *node; |
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void __iomem *base; |
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bool l2_wt_override = false; |
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#if defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH) |
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l2_wt_override = true; |
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#endif |
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node = of_find_matching_node(NULL, feroceon_ids); |
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if (node && of_device_is_compatible(node, "marvell,kirkwood-cache")) { |
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base = of_iomap(node, 0); |
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if (!base) |
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return -ENOMEM; |
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if (l2_wt_override) |
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writel(readl(base) | L2_WRITETHROUGH_KIRKWOOD, base); |
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else |
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writel(readl(base) & ~L2_WRITETHROUGH_KIRKWOOD, base); |
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} |
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feroceon_l2_init(l2_wt_override); |
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return 0; |
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} |
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#endif
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