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43 lines
1.1 KiB
43 lines
1.1 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* This file contains common function prototypes to avoid externs |
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* in the c files. |
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* |
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* Copyright (C) 2011 Xilinx |
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*/ |
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#ifndef __MACH_ZYNQ_COMMON_H__ |
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#define __MACH_ZYNQ_COMMON_H__ |
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extern int zynq_slcr_init(void); |
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extern int zynq_early_slcr_init(void); |
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extern void zynq_slcr_cpu_stop(int cpu); |
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extern void zynq_slcr_cpu_start(int cpu); |
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extern bool zynq_slcr_cpu_state_read(int cpu); |
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extern void zynq_slcr_cpu_state_write(int cpu, bool die); |
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extern u32 zynq_slcr_get_device_id(void); |
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#ifdef CONFIG_SMP |
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extern char zynq_secondary_trampoline; |
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extern char zynq_secondary_trampoline_jump; |
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extern char zynq_secondary_trampoline_end; |
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extern int zynq_cpun_start(u32 address, int cpu); |
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extern const struct smp_operations zynq_smp_ops; |
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#endif |
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extern void __iomem *zynq_scu_base; |
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void zynq_pm_late_init(void); |
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static inline void zynq_core_pm_init(void) |
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{ |
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/* A9 clock gating */ |
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asm volatile ("mrc p15, 0, r12, c15, c0, 0\n" |
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"orr r12, r12, #1\n" |
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"mcr p15, 0, r12, c15, c0, 0\n" |
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: /* no outputs */ |
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: /* no inputs */ |
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: "r12"); |
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} |
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#endif
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