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435 lines
10 KiB
435 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. |
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* Copyright (c) 2011, Google, Inc. |
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* |
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* Author: Colin Cross <ccross@android.com> |
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* Gary King <gking@nvidia.com> |
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*/ |
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#include <linux/linkage.h> |
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#include <soc/tegra/flowctrl.h> |
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#include <asm/assembler.h> |
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#include <asm/proc-fns.h> |
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#include <asm/cp15.h> |
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#include <asm/cache.h> |
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#include "irammap.h" |
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#include "reset.h" |
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#include "sleep.h" |
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#define EMC_CFG 0xc |
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#define EMC_ADR_CFG 0x10 |
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#define EMC_NOP 0xdc |
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#define EMC_SELF_REF 0xe0 |
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#define EMC_REQ_CTRL 0x2b0 |
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#define EMC_EMC_STATUS 0x2b4 |
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#define CLK_RESET_CCLK_BURST 0x20 |
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#define CLK_RESET_CCLK_DIVIDER 0x24 |
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#define CLK_RESET_SCLK_BURST 0x28 |
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#define CLK_RESET_SCLK_DIVIDER 0x2c |
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#define CLK_RESET_PLLC_BASE 0x80 |
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#define CLK_RESET_PLLM_BASE 0x90 |
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#define CLK_RESET_PLLP_BASE 0xa0 |
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#define APB_MISC_XM2CFGCPADCTRL 0x8c8 |
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#define APB_MISC_XM2CFGDPADCTRL 0x8cc |
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#define APB_MISC_XM2CLKCFGPADCTRL 0x8d0 |
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#define APB_MISC_XM2COMPPADCTRL 0x8d4 |
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#define APB_MISC_XM2VTTGENPADCTRL 0x8d8 |
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#define APB_MISC_XM2CFGCPADCTRL2 0x8e4 |
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#define APB_MISC_XM2CFGDPADCTRL2 0x8e8 |
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#define PLLC_STORE_MASK (1 << 0) |
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#define PLLM_STORE_MASK (1 << 1) |
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#define PLLP_STORE_MASK (1 << 2) |
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.macro test_pll_state, rd, test_mask |
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ldr \rd, tegra_pll_state |
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tst \rd, #\test_mask |
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.endm |
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.macro store_pll_state, rd, tmp, r_car_base, pll_base, pll_mask |
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ldr \rd, [\r_car_base, #\pll_base] |
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tst \rd, #(1 << 30) |
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ldr \rd, tegra_pll_state |
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biceq \rd, \rd, #\pll_mask |
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orrne \rd, \rd, #\pll_mask |
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adr \tmp, tegra_pll_state |
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str \rd, [\tmp] |
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.endm |
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.macro pll_enable, rd, r_car_base, pll_base, test_mask |
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test_pll_state \rd, \test_mask |
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beq 1f |
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ldr \rd, [\r_car_base, #\pll_base] |
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tst \rd, #(1 << 30) |
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orreq \rd, \rd, #(1 << 30) |
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streq \rd, [\r_car_base, #\pll_base] |
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1: |
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.endm |
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.macro emc_device_mask, rd, base |
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ldr \rd, [\base, #EMC_ADR_CFG] |
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tst \rd, #(0x3 << 24) |
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moveq \rd, #(0x1 << 8) @ just 1 device |
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movne \rd, #(0x3 << 8) @ 2 devices |
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.endm |
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) |
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/* |
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* tegra20_hotplug_shutdown(void) |
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* |
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* puts the current cpu in reset |
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* should never return |
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*/ |
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ENTRY(tegra20_hotplug_shutdown) |
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/* Put this CPU down */ |
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cpu_id r0 |
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bl tegra20_cpu_shutdown |
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ret lr @ should never get here |
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ENDPROC(tegra20_hotplug_shutdown) |
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/* |
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* tegra20_cpu_shutdown(int cpu) |
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* |
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* r0 is cpu to reset |
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* |
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* puts the specified CPU in wait-for-event mode on the flow controller |
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* and puts the CPU in reset |
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* can be called on the current cpu or another cpu |
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* if called on the current cpu, does not return |
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* MUST NOT BE CALLED FOR CPU 0. |
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* |
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* corrupts r0-r3, r12 |
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*/ |
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ENTRY(tegra20_cpu_shutdown) |
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cmp r0, #0 |
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reteq lr @ must not be called for CPU 0 |
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cpu_to_halt_reg r1, r0 |
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ldr r3, =TEGRA_FLOW_CTRL_VIRT |
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mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME |
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str r2, [r3, r1] @ put flow controller in wait event mode |
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ldr r2, [r3, r1] |
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isb |
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dsb |
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movw r1, 0x1011 |
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mov r1, r1, lsl r0 |
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ldr r3, =TEGRA_CLK_RESET_VIRT |
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str r1, [r3, #0x340] @ put slave CPU in reset |
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isb |
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dsb |
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cpu_id r3 |
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cmp r3, r0 |
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beq . |
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ret lr |
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ENDPROC(tegra20_cpu_shutdown) |
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#endif |
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#ifdef CONFIG_PM_SLEEP |
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/* |
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* tegra20_sleep_core_finish(unsigned long v2p) |
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* |
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* Enters suspend in LP0 or LP1 by turning off the mmu and jumping to |
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* tegra20_tear_down_core in IRAM |
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*/ |
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ENTRY(tegra20_sleep_core_finish) |
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mov r4, r0 |
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/* Flush, disable the L1 data cache and exit SMP */ |
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mov r0, #TEGRA_FLUSH_CACHE_ALL |
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bl tegra_disable_clean_inv_dcache |
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mov r0, r4 |
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mov32 r3, tegra_shut_off_mmu |
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add r3, r3, r0 |
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mov32 r0, tegra20_tear_down_core |
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mov32 r1, tegra20_iram_start |
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sub r0, r0, r1 |
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mov32 r1, TEGRA_IRAM_LPx_RESUME_AREA |
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add r0, r0, r1 |
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ret r3 |
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ENDPROC(tegra20_sleep_core_finish) |
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/* |
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* tegra20_tear_down_cpu |
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* |
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* Switches the CPU cluster to PLL-P and enters sleep. |
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*/ |
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ENTRY(tegra20_tear_down_cpu) |
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bl tegra_switch_cpu_to_pllp |
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b tegra20_enter_sleep |
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ENDPROC(tegra20_tear_down_cpu) |
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/* START OF ROUTINES COPIED TO IRAM */ |
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.align L1_CACHE_SHIFT |
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.globl tegra20_iram_start |
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tegra20_iram_start: |
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/* |
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* tegra20_lp1_reset |
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* |
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* reset vector for LP1 restore; copied into IRAM during suspend. |
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* Brings the system back up to a safe staring point (SDRAM out of |
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* self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP, |
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* system clock running on the same PLL that it suspended at), and |
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* jumps to tegra_resume to restore virtual addressing and PLLX. |
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* The physical address of tegra_resume expected to be stored in |
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* PMC_SCRATCH41. |
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* |
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* NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA. |
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*/ |
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ENTRY(tegra20_lp1_reset) |
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/* |
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* The CPU and system bus are running at 32KHz and executing from |
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* IRAM when this code is executed; immediately switch to CLKM and |
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* enable PLLM, PLLP, PLLC. |
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*/ |
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mov32 r0, TEGRA_CLK_RESET_BASE |
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mov r1, #(1 << 28) |
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str r1, [r0, #CLK_RESET_SCLK_BURST] |
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str r1, [r0, #CLK_RESET_CCLK_BURST] |
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mov r1, #0 |
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str r1, [r0, #CLK_RESET_CCLK_DIVIDER] |
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str r1, [r0, #CLK_RESET_SCLK_DIVIDER] |
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pll_enable r1, r0, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK |
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pll_enable r1, r0, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK |
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pll_enable r1, r0, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK |
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adr r2, tegra20_sdram_pad_address |
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adr r4, tegra20_sdram_pad_save |
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mov r5, #0 |
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ldr r6, tegra20_sdram_pad_size |
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padload: |
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ldr r7, [r2, r5] @ r7 is the addr in the pad_address |
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ldr r1, [r4, r5] |
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str r1, [r7] @ restore the value in pad_save |
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add r5, r5, #4 |
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cmp r6, r5 |
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bne padload |
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padload_done: |
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/* 255uS delay for PLL stabilization */ |
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mov32 r7, TEGRA_TMRUS_BASE |
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ldr r1, [r7] |
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add r1, r1, #0xff |
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wait_until r1, r7, r9 |
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adr r4, tegra20_sclk_save |
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ldr r4, [r4] |
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str r4, [r0, #CLK_RESET_SCLK_BURST] |
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mov32 r4, ((1 << 28) | (4)) @ burst policy is PLLP |
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str r4, [r0, #CLK_RESET_CCLK_BURST] |
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mov32 r0, TEGRA_EMC_BASE |
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ldr r1, [r0, #EMC_CFG] |
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bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP |
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str r1, [r0, #EMC_CFG] |
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mov r1, #0 |
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str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh |
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mov r1, #1 |
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str r1, [r0, #EMC_NOP] |
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str r1, [r0, #EMC_NOP] |
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emc_device_mask r1, r0 |
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exit_selfrefresh_loop: |
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ldr r2, [r0, #EMC_EMC_STATUS] |
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ands r2, r2, r1 |
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bne exit_selfrefresh_loop |
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mov r1, #0 @ unstall all transactions |
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str r1, [r0, #EMC_REQ_CTRL] |
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mov32 r0, TEGRA_PMC_BASE |
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ldr r0, [r0, #PMC_SCRATCH41] |
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ret r0 @ jump to tegra_resume |
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ENDPROC(tegra20_lp1_reset) |
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/* |
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* tegra20_tear_down_core |
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* |
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* copied into and executed from IRAM |
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* puts memory in self-refresh for LP0 and LP1 |
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*/ |
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tegra20_tear_down_core: |
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bl tegra20_sdram_self_refresh |
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bl tegra20_switch_cpu_to_clk32k |
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b tegra20_enter_sleep |
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/* |
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* tegra20_switch_cpu_to_clk32k |
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* |
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* In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock |
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* to the 32KHz clock. |
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*/ |
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tegra20_switch_cpu_to_clk32k: |
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/* |
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* start by switching to CLKM to safely disable PLLs, then switch to |
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* CLKS. |
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*/ |
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mov r0, #(1 << 28) |
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str r0, [r5, #CLK_RESET_SCLK_BURST] |
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str r0, [r5, #CLK_RESET_CCLK_BURST] |
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mov r0, #0 |
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str r0, [r5, #CLK_RESET_CCLK_DIVIDER] |
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str r0, [r5, #CLK_RESET_SCLK_DIVIDER] |
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/* 2uS delay delay between changing SCLK and disabling PLLs */ |
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mov32 r7, TEGRA_TMRUS_BASE |
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ldr r1, [r7] |
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add r1, r1, #2 |
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wait_until r1, r7, r9 |
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store_pll_state r0, r1, r5, CLK_RESET_PLLC_BASE, PLLC_STORE_MASK |
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store_pll_state r0, r1, r5, CLK_RESET_PLLM_BASE, PLLM_STORE_MASK |
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store_pll_state r0, r1, r5, CLK_RESET_PLLP_BASE, PLLP_STORE_MASK |
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/* disable PLLM, PLLP and PLLC */ |
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ldr r0, [r5, #CLK_RESET_PLLM_BASE] |
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bic r0, r0, #(1 << 30) |
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str r0, [r5, #CLK_RESET_PLLM_BASE] |
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ldr r0, [r5, #CLK_RESET_PLLP_BASE] |
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bic r0, r0, #(1 << 30) |
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str r0, [r5, #CLK_RESET_PLLP_BASE] |
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ldr r0, [r5, #CLK_RESET_PLLC_BASE] |
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bic r0, r0, #(1 << 30) |
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str r0, [r5, #CLK_RESET_PLLC_BASE] |
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/* switch to CLKS */ |
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mov r0, #0 /* brust policy = 32KHz */ |
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str r0, [r5, #CLK_RESET_SCLK_BURST] |
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ret lr |
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/* |
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* tegra20_enter_sleep |
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* |
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* uses flow controller to enter sleep state |
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* executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1 |
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* executes from SDRAM with target state is LP2 |
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*/ |
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tegra20_enter_sleep: |
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mov32 r6, TEGRA_FLOW_CTRL_BASE |
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mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT |
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orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ |
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cpu_id r1 |
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cpu_to_halt_reg r1, r1 |
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str r0, [r6, r1] |
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dsb |
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ldr r0, [r6, r1] /* memory barrier */ |
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halted: |
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dsb |
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wfe /* CPU should be power gated here */ |
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isb |
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b halted |
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/* |
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* tegra20_sdram_self_refresh |
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* |
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* called with MMU off and caches disabled |
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* puts sdram in self refresh |
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* must be executed from IRAM |
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*/ |
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tegra20_sdram_self_refresh: |
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mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr |
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mov r2, #3 |
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str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests |
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emcidle: |
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ldr r2, [r1, #EMC_EMC_STATUS] |
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tst r2, #4 |
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beq emcidle |
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mov r2, #1 |
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str r2, [r1, #EMC_SELF_REF] |
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emc_device_mask r2, r1 |
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emcself: |
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ldr r3, [r1, #EMC_EMC_STATUS] |
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and r3, r3, r2 |
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cmp r3, r2 |
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bne emcself @ loop until DDR in self-refresh |
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adr r2, tegra20_sdram_pad_address |
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adr r3, tegra20_sdram_pad_safe |
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adr r4, tegra20_sdram_pad_save |
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mov r5, #0 |
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ldr r6, tegra20_sdram_pad_size |
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padsave: |
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ldr r0, [r2, r5] @ r0 is the addr in the pad_address |
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ldr r1, [r0] |
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str r1, [r4, r5] @ save the content of the addr |
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ldr r1, [r3, r5] |
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str r1, [r0] @ set the save val to the addr |
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add r5, r5, #4 |
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cmp r6, r5 |
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bne padsave |
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padsave_done: |
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mov32 r5, TEGRA_CLK_RESET_BASE |
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ldr r0, [r5, #CLK_RESET_SCLK_BURST] |
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adr r2, tegra20_sclk_save |
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str r0, [r2] |
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dsb |
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ret lr |
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tegra20_sdram_pad_address: |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2CLKCFGPADCTRL |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2COMPPADCTRL |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2VTTGENPADCTRL |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL2 |
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.word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL2 |
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tegra20_sdram_pad_size: |
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.word tegra20_sdram_pad_size - tegra20_sdram_pad_address |
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tegra20_sdram_pad_safe: |
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.word 0x8 |
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.word 0x8 |
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.word 0x0 |
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.word 0x8 |
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.word 0x5500 |
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.word 0x08080040 |
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.word 0x0 |
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tegra20_sclk_save: |
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.word 0x0 |
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tegra20_sdram_pad_save: |
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.rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4 |
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.long 0 |
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.endr |
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tegra_pll_state: |
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.word 0x0 |
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.ltorg |
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/* dummy symbol for end of IRAM */ |
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.align L1_CACHE_SHIFT |
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.globl tegra20_iram_end |
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tegra20_iram_end: |
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b . |
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#endif
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