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301 lines
6.9 KiB
301 lines
6.9 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright (c) 2012, NVIDIA Corporation. All rights reserved. |
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*/ |
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#include <linux/init.h> |
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#include <linux/linkage.h> |
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#include <soc/tegra/flowctrl.h> |
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#include <soc/tegra/fuse.h> |
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#include <asm/assembler.h> |
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#include <asm/asm-offsets.h> |
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#include <asm/cache.h> |
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#include "iomap.h" |
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#include "reset.h" |
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#include "sleep.h" |
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#define PMC_SCRATCH41 0x140 |
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#ifdef CONFIG_PM_SLEEP |
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/* |
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* tegra_resume |
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* |
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* CPU boot vector when restarting the a CPU following |
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* an LP2 transition. Also branched to by LP0 and LP1 resume after |
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* re-enabling sdram. |
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* |
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* r6: SoC ID |
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* r8: CPU part number |
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*/ |
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ENTRY(tegra_resume) |
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check_cpu_part_num 0xc09, r8, r9 |
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bleq v7_invalidate_l1 |
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cpu_id r0 |
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cmp r0, #0 @ CPU0? |
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THUMB( it ne ) |
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bne cpu_resume @ no |
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 |
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/* Are we on Tegra20? */ |
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cmp r6, #TEGRA20 |
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beq 1f @ Yes |
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/* Clear the flow controller flags for this CPU. */ |
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cpu_to_csr_reg r3, r0 |
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mov32 r2, TEGRA_FLOW_CTRL_BASE |
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ldr r1, [r2, r3] |
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/* Clear event & intr flag */ |
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orr r1, r1, \ |
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#FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG |
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movw r0, #0x3FFD @ enable, cluster_switch, immed, bitmaps |
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@ & ext flags for CPU power mgnt |
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bic r1, r1, r0 |
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str r1, [r2, r3] |
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1: |
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mov32 r9, 0xc09 |
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cmp r8, r9 |
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bne end_ca9_scu_l2_resume |
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#ifdef CONFIG_HAVE_ARM_SCU |
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/* enable SCU */ |
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mov32 r0, TEGRA_ARM_PERIF_BASE |
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ldr r1, [r0] |
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orr r1, r1, #1 |
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str r1, [r0] |
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#endif |
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bl tegra_resume_trusted_foundations |
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#ifdef CONFIG_CACHE_L2X0 |
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/* L2 cache resume & re-enable */ |
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bl l2c310_early_resume |
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#endif |
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end_ca9_scu_l2_resume: |
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mov32 r9, 0xc0f |
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cmp r8, r9 |
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bleq tegra_init_l2_for_a15 |
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b cpu_resume |
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ENDPROC(tegra_resume) |
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/* |
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* tegra_resume_trusted_foundations |
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* |
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* Trusted Foundations firmware initialization. |
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* |
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* Doesn't return if firmware presents. |
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* Corrupted registers: r1, r2 |
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*/ |
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ENTRY(tegra_resume_trusted_foundations) |
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/* Check whether Trusted Foundations firmware presents. */ |
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mov32 r2, TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET |
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ldr r1, =__tegra_cpu_reset_handler_data_offset + \ |
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RESET_DATA(TF_PRESENT) |
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ldr r1, [r2, r1] |
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cmp r1, #0 |
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reteq lr |
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.arch_extension sec |
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/* |
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* First call after suspend wakes firmware. No arguments required |
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* for some firmware versions. Downstream kernel of ASUS TF300T uses |
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* r0=3 for the wake-up notification. |
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*/ |
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mov r0, #3 |
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smc #0 |
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b cpu_resume |
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ENDPROC(tegra_resume_trusted_foundations) |
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#endif |
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.align L1_CACHE_SHIFT |
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ENTRY(__tegra_cpu_reset_handler_start) |
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/* |
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* __tegra_cpu_reset_handler: |
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* |
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* Common handler for all CPU reset events. |
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* |
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* Register usage within the reset handler: |
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* |
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* Others: scratch |
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* R6 = SoC ID |
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* R7 = CPU present (to the OS) mask |
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* R8 = CPU in LP1 state mask |
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* R9 = CPU in LP2 state mask |
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* R10 = CPU number |
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* R11 = CPU mask |
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* R12 = pointer to reset handler data |
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* |
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* NOTE: This code is copied to IRAM. All code and data accesses |
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* must be position-independent. |
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*/ |
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.arm |
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.align L1_CACHE_SHIFT |
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ENTRY(__tegra_cpu_reset_handler) |
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cpsid aif, 0x13 @ SVC mode, interrupts disabled |
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tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 |
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adr r12, __tegra_cpu_reset_handler_data |
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ldr r5, [r12, #RESET_DATA(TF_PRESENT)] |
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cmp r5, #0 |
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bne after_errata |
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
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t20_check: |
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cmp r6, #TEGRA20 |
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bne after_t20_check |
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t20_errata: |
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# Tegra20 is a Cortex-A9 r1p1 |
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mrc p15, 0, r0, c1, c0, 0 @ read system control register |
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orr r0, r0, #1 << 14 @ erratum 716044 |
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mcr p15, 0, r0, c1, c0, 0 @ write system control register |
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
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orr r0, r0, #1 << 4 @ erratum 742230 |
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orr r0, r0, #1 << 11 @ erratum 751472 |
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
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b after_errata |
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after_t20_check: |
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#endif |
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC |
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t30_check: |
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cmp r6, #TEGRA30 |
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bne after_t30_check |
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t30_errata: |
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# Tegra30 is a Cortex-A9 r2p9 |
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register |
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orr r0, r0, #1 << 6 @ erratum 743622 |
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orr r0, r0, #1 << 11 @ erratum 751472 |
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register |
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b after_errata |
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after_t30_check: |
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#endif |
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after_errata: |
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mrc p15, 0, r10, c0, c0, 5 @ MPIDR |
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and r10, r10, #0x3 @ R10 = CPU number |
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mov r11, #1 |
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mov r11, r11, lsl r10 @ R11 = CPU mask |
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#ifdef CONFIG_SMP |
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/* Does the OS know about this CPU? */ |
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ldr r7, [r12, #RESET_DATA(MASK_PRESENT)] |
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tst r7, r11 @ if !present |
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bleq __die @ CPU not present (to OS) |
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#endif |
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/* Waking up from LP1? */ |
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ldr r8, [r12, #RESET_DATA(MASK_LP1)] |
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tst r8, r11 @ if in_lp1 |
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beq __is_not_lp1 |
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cmp r10, #0 |
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bne __die @ only CPU0 can be here |
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ldr lr, [r12, #RESET_DATA(STARTUP_LP1)] |
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cmp lr, #0 |
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bleq __die @ no LP1 startup handler |
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THUMB( add lr, lr, #1 ) @ switch to Thumb mode |
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bx lr |
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__is_not_lp1: |
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/* Waking up from LP2? */ |
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ldr r9, [r12, #RESET_DATA(MASK_LP2)] |
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tst r9, r11 @ if in_lp2 |
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beq __is_not_lp2 |
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ldr lr, [r12, #RESET_DATA(STARTUP_LP2)] |
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cmp lr, #0 |
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bleq __die @ no LP2 startup handler |
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bx lr |
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__is_not_lp2: |
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#ifdef CONFIG_SMP |
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/* |
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* Can only be secondary boot (initial or hotplug) |
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* CPU0 can't be here for Tegra20/30 |
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*/ |
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cmp r6, #TEGRA114 |
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beq __no_cpu0_chk |
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cmp r10, #0 |
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bleq __die @ CPU0 cannot be here |
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__no_cpu0_chk: |
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ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)] |
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cmp lr, #0 |
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bleq __die @ no secondary startup handler |
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bx lr |
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#endif |
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/* |
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* We don't know why the CPU reset. Just kill it. |
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* The LR register will contain the address we died at + 4. |
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*/ |
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__die: |
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sub lr, lr, #4 |
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mov32 r7, TEGRA_PMC_BASE |
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str lr, [r7, #PMC_SCRATCH41] |
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mov32 r7, TEGRA_CLK_RESET_BASE |
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/* Are we on Tegra20? */ |
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cmp r6, #TEGRA20 |
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bne 1f |
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#ifdef CONFIG_ARCH_TEGRA_2x_SOC |
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mov32 r0, 0x1111 |
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mov r1, r0, lsl r10 |
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str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET |
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#endif |
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1: |
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC |
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mov32 r6, TEGRA_FLOW_CTRL_BASE |
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cmp r10, #0 |
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moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS |
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moveq r2, #FLOW_CTRL_CPU0_CSR |
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movne r1, r10, lsl #3 |
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addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8) |
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addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8) |
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/* Clear CPU "event" and "interrupt" flags and power gate |
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it when halting but not before it is in the "WFI" state. */ |
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ldr r0, [r6, +r2] |
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orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG |
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orr r0, r0, #FLOW_CTRL_CSR_ENABLE |
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str r0, [r6, +r2] |
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/* Unconditionally halt this CPU */ |
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mov r0, #FLOW_CTRL_WAITEVENT |
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str r0, [r6, +r1] |
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ldr r0, [r6, +r1] @ memory barrier |
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dsb |
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isb |
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wfi @ CPU should be power gated here |
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/* If the CPU didn't power gate above just kill it's clock. */ |
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mov r0, r11, lsl #8 |
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str r0, [r7, #348] @ CLK_CPU_CMPLX_SET |
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#endif |
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/* If the CPU still isn't dead, just spin here. */ |
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b . |
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ENDPROC(__tegra_cpu_reset_handler) |
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.align L1_CACHE_SHIFT |
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.type __tegra_cpu_reset_handler_data, %object |
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.globl __tegra_cpu_reset_handler_data |
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.globl __tegra_cpu_reset_handler_data_offset |
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.equ __tegra_cpu_reset_handler_data_offset, \ |
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. - __tegra_cpu_reset_handler_start |
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__tegra_cpu_reset_handler_data: |
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.rept TEGRA_RESET_DATA_SIZE |
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.long 0 |
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.endr |
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.align L1_CACHE_SHIFT |
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ENTRY(__tegra_cpu_reset_handler_end)
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