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110 lines
2.9 KiB
110 lines
2.9 KiB
/* |
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* arch/arm/mach-spear3xx/spear3xx.c |
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* |
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* SPEAr3XX machines common source file |
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* |
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* Copyright (C) 2009-2012 ST Microelectronics |
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* Viresh Kumar <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#define pr_fmt(fmt) "SPEAr3xx: " fmt |
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#include <linux/amba/pl022.h> |
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#include <linux/amba/pl080.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <asm/mach/map.h> |
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#include "pl080.h" |
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#include "generic.h" |
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#include <mach/spear.h> |
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#include <mach/misc_regs.h> |
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/* ssp device registration */ |
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struct pl022_ssp_controller pl022_plat_data = { |
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.bus_id = 0, |
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.enable_dma = 1, |
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.dma_filter = pl08x_filter_id, |
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.dma_tx_param = "ssp0_tx", |
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.dma_rx_param = "ssp0_rx", |
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/* |
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* This is number of spi devices that can be connected to spi. There are |
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* two type of chipselects on which slave devices can work. One is chip |
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* select provided by spi masters other is controlled through external |
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* gpio's. We can't use chipselect provided from spi master (because as |
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* soon as FIFO becomes empty, CS is disabled and transfer ends). So |
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* this number now depends on number of gpios available for spi. each |
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* slave on each master requires a separate gpio pin. |
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*/ |
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.num_chipselect = 2, |
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}; |
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/* dmac device registration */ |
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struct pl08x_platform_data pl080_plat_data = { |
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.memcpy_burst_size = PL08X_BURST_SZ_16, |
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.memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS, |
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.memcpy_prot_buff = true, |
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.memcpy_prot_cache = true, |
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.lli_buses = PL08X_AHB1, |
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.mem_buses = PL08X_AHB1, |
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.get_xfer_signal = pl080_get_signal, |
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.put_xfer_signal = pl080_put_signal, |
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}; |
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/* |
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* Following will create 16MB static virtual/physical mappings |
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* PHYSICAL VIRTUAL |
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* 0xD0000000 0xFD000000 |
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* 0xFC000000 0xFC000000 |
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*/ |
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struct map_desc spear3xx_io_desc[] __initdata = { |
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{ |
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.virtual = (unsigned long)VA_SPEAR_ICM1_2_BASE, |
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.pfn = __phys_to_pfn(SPEAR_ICM1_2_BASE), |
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.length = SZ_16M, |
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.type = MT_DEVICE |
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}, { |
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.virtual = (unsigned long)VA_SPEAR_ICM3_SMI_CTRL_BASE, |
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.pfn = __phys_to_pfn(SPEAR_ICM3_SMI_CTRL_BASE), |
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.length = SZ_16M, |
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.type = MT_DEVICE |
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}, |
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}; |
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/* This will create static memory mapping for selected devices */ |
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void __init spear3xx_map_io(void) |
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{ |
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iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); |
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} |
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void __init spear3xx_timer_init(void) |
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{ |
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char pclk_name[] = "pll3_clk"; |
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struct clk *gpt_clk, *pclk; |
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spear3xx_clk_init(MISC_BASE, VA_SPEAR320_SOC_CONFIG_BASE); |
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/* get the system timer clock */ |
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gpt_clk = clk_get_sys("gpt0", NULL); |
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if (IS_ERR(gpt_clk)) { |
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pr_err("%s:couldn't get clk for gpt\n", __func__); |
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BUG(); |
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} |
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/* get the suitable parent clock for timer*/ |
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pclk = clk_get(NULL, pclk_name); |
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if (IS_ERR(pclk)) { |
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pr_err("%s:couldn't get %s as parent for gpt\n", |
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__func__, pclk_name); |
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BUG(); |
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} |
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clk_set_parent(gpt_clk, pclk); |
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clk_put(gpt_clk); |
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clk_put(pclk); |
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spear_setup_of_timer(); |
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}
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