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60 lines
1.7 KiB
60 lines
1.7 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* r8a7779 processor support |
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* |
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* Copyright (C) 2011, 2013 Renesas Solutions Corp. |
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* Copyright (C) 2011 Magnus Damm |
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* Copyright (C) 2013 Cogent Embedded, Inc. |
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*/ |
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#include <linux/init.h> |
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#include <linux/irqchip.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include "common.h" |
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#include "r8a7779.h" |
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#define HPBREG_BASE 0xfe700000 |
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/* IRQ */ |
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#define INT2SMSKCR0 0x822a0 /* Interrupt Submask Clear Register 0 */ |
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#define INT2SMSKCR1 0x822a4 /* Interrupt Submask Clear Register 1 */ |
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#define INT2SMSKCR2 0x822a8 /* Interrupt Submask Clear Register 2 */ |
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#define INT2SMSKCR3 0x822ac /* Interrupt Submask Clear Register 3 */ |
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#define INT2SMSKCR4 0x822b0 /* Interrupt Submask Clear Register 4 */ |
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#define INT2NTSR0 0x00060 /* Interrupt Notification Select Register 0 */ |
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#define INT2NTSR1 0x00064 /* Interrupt Notification Select Register 1 */ |
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static void __init r8a7779_init_irq_dt(void) |
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{ |
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void __iomem *base = ioremap(HPBREG_BASE, 0x00100000); |
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irqchip_init(); |
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/* route all interrupts to ARM */ |
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writel(0xffffffff, base + INT2NTSR0); |
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writel(0x3fffffff, base + INT2NTSR1); |
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/* unmask all known interrupts in INTCS2 */ |
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writel(0xfffffff0, base + INT2SMSKCR0); |
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writel(0xfff7ffff, base + INT2SMSKCR1); |
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writel(0xfffbffdf, base + INT2SMSKCR2); |
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writel(0xbffffffc, base + INT2SMSKCR3); |
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writel(0x003fee3f, base + INT2SMSKCR4); |
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iounmap(base); |
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} |
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static const char *const r8a7779_compat_dt[] __initconst = { |
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"renesas,r8a7779", |
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NULL, |
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}; |
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DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)") |
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.smp = smp_ops(r8a7779_smp_ops), |
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.init_irq = r8a7779_init_irq_dt, |
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.init_late = shmobile_init_late, |
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.dt_compat = r8a7779_compat_dt, |
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MACHINE_END
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