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147 lines
3.0 KiB
147 lines
3.0 KiB
/* SPDX-License-Identifier: GPL-2.0 |
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* |
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* SMP support for R-Mobile / SH-Mobile |
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* |
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* Copyright (C) 2010 Magnus Damm |
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* Copyright (C) 2010 Takashi Yoshii |
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* |
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* Based on vexpress, Copyright (c) 2003 ARM Limited, All Rights Reserved |
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*/ |
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#include <linux/init.h> |
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#include <linux/linkage.h> |
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#include <linux/threads.h> |
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#include <asm/assembler.h> |
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#include <asm/memory.h> |
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#define SCTLR_MMU 0x01 |
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#define BOOTROM_ADDRESS 0xE6340000 |
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#define RWTCSRA_ADDRESS 0xE6020004 |
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#define RWTCSRA_WOVF 0x10 |
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/* |
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* Reset vector for secondary CPUs. |
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* This will be mapped at address 0 by SBAR register. |
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* We need _long_ jump to the physical address. |
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*/ |
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.arm |
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.align 12 |
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ENTRY(shmobile_boot_vector) |
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ldr r1, 1f |
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bx r1 |
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ENDPROC(shmobile_boot_vector) |
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.align 2 |
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.globl shmobile_boot_fn |
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shmobile_boot_fn: |
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1: .space 4 |
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.globl shmobile_boot_size |
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shmobile_boot_size: |
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.long . - shmobile_boot_vector |
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#ifdef CONFIG_ARCH_RCAR_GEN2 |
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/* |
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* Reset vector for R-Car Gen2 and RZ/G1 secondary CPUs. |
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* This will be mapped at address 0 by SBAR register. |
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*/ |
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ENTRY(shmobile_boot_vector_gen2) |
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mrc p15, 0, r0, c0, c0, 5 @ r0 = MPIDR |
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ldr r1, shmobile_boot_cpu_gen2 |
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cmp r0, r1 |
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bne shmobile_smp_continue_gen2 |
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mrc p15, 0, r1, c1, c0, 0 @ r1 = SCTLR |
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and r0, r1, #SCTLR_MMU |
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cmp r0, #SCTLR_MMU |
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beq shmobile_smp_continue_gen2 |
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ldr r0, rwtcsra |
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mov r1, #0 |
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ldrb r1, [r0] |
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and r0, r1, #RWTCSRA_WOVF |
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cmp r0, #RWTCSRA_WOVF |
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bne shmobile_smp_continue_gen2 |
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ldr r0, bootrom |
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bx r0 |
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shmobile_smp_continue_gen2: |
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ldr r1, shmobile_boot_fn_gen2 |
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bx r1 |
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ENDPROC(shmobile_boot_vector_gen2) |
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.align 4 |
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rwtcsra: |
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.word RWTCSRA_ADDRESS |
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bootrom: |
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.word BOOTROM_ADDRESS |
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.globl shmobile_boot_cpu_gen2 |
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shmobile_boot_cpu_gen2: |
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.word 0x00000000 |
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.align 2 |
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.globl shmobile_boot_fn_gen2 |
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shmobile_boot_fn_gen2: |
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.space 4 |
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.globl shmobile_boot_size_gen2 |
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shmobile_boot_size_gen2: |
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.long . - shmobile_boot_vector_gen2 |
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#endif /* CONFIG_ARCH_RCAR_GEN2 */ |
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/* |
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* Per-CPU SMP boot function/argument selection code based on MPIDR |
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*/ |
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ENTRY(shmobile_smp_boot) |
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mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR |
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and r0, r1, #0xffffff @ MPIDR_HWID_BITMASK |
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@ r0 = cpu_logical_map() value |
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mov r1, #0 @ r1 = CPU index |
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adr r2, 1f |
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ldmia r2, {r5, r6, r7} |
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add r5, r5, r2 @ array of per-cpu mpidr values |
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add r6, r6, r2 @ array of per-cpu functions |
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add r7, r7, r2 @ array of per-cpu arguments |
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shmobile_smp_boot_find_mpidr: |
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ldr r8, [r5, r1, lsl #2] |
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cmp r8, r0 |
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bne shmobile_smp_boot_next |
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ldr r9, [r6, r1, lsl #2] |
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cmp r9, #0 |
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bne shmobile_smp_boot_found |
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shmobile_smp_boot_next: |
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add r1, r1, #1 |
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cmp r1, #NR_CPUS |
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blo shmobile_smp_boot_find_mpidr |
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b shmobile_smp_sleep |
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shmobile_smp_boot_found: |
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ldr r0, [r7, r1, lsl #2] |
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ret r9 |
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ENDPROC(shmobile_smp_boot) |
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ENTRY(shmobile_smp_sleep) |
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wfi |
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b shmobile_smp_boot |
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ENDPROC(shmobile_smp_sleep) |
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.align 2 |
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1: .long shmobile_smp_mpidr - . |
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.long shmobile_smp_fn - 1b |
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.long shmobile_smp_arg - 1b |
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.bss |
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.globl shmobile_smp_mpidr |
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shmobile_smp_mpidr: |
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.space NR_CPUS * 4 |
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.globl shmobile_smp_fn |
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shmobile_smp_fn: |
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.space NR_CPUS * 4 |
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.globl shmobile_smp_arg |
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shmobile_smp_arg: |
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.space NR_CPUS * 4
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