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191 lines
6.6 KiB
191 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* linux/arch/arm/mach-sa1100/pci-nanoengine.c |
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* |
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* PCI functions for BSE nanoEngine PCI |
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* |
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* Copyright (C) 2010 Marcelo Roberto Jimenez <[email protected]> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/irq.h> |
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#include <linux/pci.h> |
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#include <asm/mach/pci.h> |
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#include <asm/mach-types.h> |
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#include <mach/nanoengine.h> |
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#include <mach/hardware.h> |
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static void __iomem *nanoengine_pci_map_bus(struct pci_bus *bus, |
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unsigned int devfn, int where) |
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{ |
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if (bus->number != 0 || (devfn >> 3) != 0) |
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return NULL; |
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return (void __iomem *)NANO_PCI_CONFIG_SPACE_VIRT + |
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((bus->number << 16) | (devfn << 8) | (where & ~3)); |
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} |
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static struct pci_ops pci_nano_ops = { |
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.map_bus = nanoengine_pci_map_bus, |
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.read = pci_generic_config_read32, |
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.write = pci_generic_config_write32, |
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}; |
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static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot, |
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u8 pin) |
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{ |
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return NANOENGINE_IRQ_GPIO_PCI; |
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} |
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static struct resource pci_io_ports = |
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DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); |
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static struct resource pci_non_prefetchable_memory = { |
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.name = "PCI non-prefetchable", |
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.start = NANO_PCI_MEM_RW_PHYS, |
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/* nanoEngine documentation says there is a 1 Megabyte window here, |
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* but PCI reports just 128 + 8 kbytes. */ |
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.end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1, |
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/* .end = NANO_PCI_MEM_RW_PHYS + SZ_128K + SZ_8K - 1,*/ |
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.flags = IORESOURCE_MEM, |
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}; |
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/* |
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* nanoEngine PCI reports 1 Megabyte of prefetchable memory, but it |
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* overlaps with previously defined memory. |
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* |
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* Here is what happens: |
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* |
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# dmesg |
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... |
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pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 |
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pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] |
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pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] |
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pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] |
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pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] |
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pci 0000:00:00.0: supports D1 D2 |
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pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot |
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pci 0000:00:00.0: PME# disabled |
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PCI: bus0: Fast back to back transfers enabled |
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pci 0000:00:00.0: BAR 6: can't assign mem pref (size 0x100000) |
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pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] |
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pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) |
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pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] |
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pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) |
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pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] |
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pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) |
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* |
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* On the other hand, if we do not request the prefetchable memory resource, |
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* linux will alloc it first and the two non-prefetchable memory areas that |
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* are our real interest will not be mapped. So we choose to map it to an |
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* unused area. It gets recognized as expansion ROM, but becomes disabled. |
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* |
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* Here is what happens then: |
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* |
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# dmesg |
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... |
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pci 0000:00:00.0: [8086:1209] type 0 class 0x000200 |
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pci 0000:00:00.0: reg 10: [mem 0x00021000-0x00021fff] |
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pci 0000:00:00.0: reg 14: [io 0x0000-0x003f] |
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pci 0000:00:00.0: reg 18: [mem 0x00000000-0x0001ffff] |
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pci 0000:00:00.0: reg 30: [mem 0x00000000-0x000fffff pref] |
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pci 0000:00:00.0: supports D1 D2 |
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pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot |
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pci 0000:00:00.0: PME# disabled |
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PCI: bus0: Fast back to back transfers enabled |
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pci 0000:00:00.0: BAR 6: assigned [mem 0x78000000-0x780fffff pref] |
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pci 0000:00:00.0: BAR 2: assigned [mem 0x18600000-0x1861ffff] |
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pci 0000:00:00.0: BAR 2: set to [mem 0x18600000-0x1861ffff] (PCI address [0x0-0x1ffff]) |
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pci 0000:00:00.0: BAR 0: assigned [mem 0x18620000-0x18620fff] |
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pci 0000:00:00.0: BAR 0: set to [mem 0x18620000-0x18620fff] (PCI address [0x20000-0x20fff]) |
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pci 0000:00:00.0: BAR 1: assigned [io 0x0400-0x043f] |
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pci 0000:00:00.0: BAR 1: set to [io 0x0400-0x043f] (PCI address [0x0-0x3f]) |
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# lspci -vv -s 0000:00:00.0 |
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00:00.0 Class 0200: Device 8086:1209 (rev 09) |
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Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx- |
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Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR+ <PERR+ INTx- |
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Latency: 0 (2000ns min, 14000ns max), Cache Line Size: 32 bytes |
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Interrupt: pin A routed to IRQ 0 |
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Region 0: Memory at 18620000 (32-bit, non-prefetchable) [size=4K] |
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Region 1: I/O ports at 0400 [size=64] |
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Region 2: [virtual] Memory at 18600000 (32-bit, non-prefetchable) [size=128K] |
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[virtual] Expansion ROM at 78000000 [disabled] [size=1M] |
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Capabilities: [dc] Power Management version 2 |
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Flags: PMEClk- DSI+ D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) |
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Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- |
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Kernel driver in use: e100 |
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Kernel modules: e100 |
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* |
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*/ |
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static struct resource pci_prefetchable_memory = { |
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.name = "PCI prefetchable", |
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.start = 0x78000000, |
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.end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1, |
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.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, |
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}; |
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static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) |
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{ |
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if (request_resource(&ioport_resource, &pci_io_ports)) { |
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printk(KERN_ERR "PCI: unable to allocate io port region\n"); |
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return -EBUSY; |
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} |
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if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) { |
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release_resource(&pci_io_ports); |
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printk(KERN_ERR "PCI: unable to allocate non prefetchable\n"); |
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return -EBUSY; |
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} |
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if (request_resource(&iomem_resource, &pci_prefetchable_memory)) { |
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release_resource(&pci_io_ports); |
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release_resource(&pci_non_prefetchable_memory); |
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printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); |
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return -EBUSY; |
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} |
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pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset); |
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pci_add_resource_offset(&sys->resources, |
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&pci_non_prefetchable_memory, sys->mem_offset); |
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pci_add_resource_offset(&sys->resources, |
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&pci_prefetchable_memory, sys->mem_offset); |
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return 1; |
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} |
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int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys) |
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{ |
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int ret = 0; |
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pcibios_min_io = 0; |
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pcibios_min_mem = 0; |
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if (nr == 0) { |
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sys->mem_offset = NANO_PCI_MEM_RW_PHYS; |
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sys->io_offset = 0x400; |
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ret = pci_nanoengine_setup_resources(sys); |
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/* Enable alternate memory bus master mode, see |
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* "Intel StrongARM SA1110 Developer's Manual", |
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* section 10.8, "Alternate Memory Bus Master Mode". */ |
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GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT; |
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GAFR |= GPIO_MBGNT | GPIO_MBREQ; |
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TUCR |= TUCR_MBGPIO; |
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} |
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return ret; |
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} |
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static struct hw_pci nanoengine_pci __initdata = { |
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.map_irq = pci_nanoengine_map_irq, |
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.nr_controllers = 1, |
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.ops = &pci_nano_ops, |
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.setup = pci_nanoengine_setup, |
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}; |
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static int __init nanoengine_pci_init(void) |
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{ |
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if (machine_is_nanoengine()) |
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pci_common_init(&nanoengine_pci); |
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return 0; |
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} |
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subsys_initcall(nanoengine_pci_init);
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