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380 lines
12 KiB
380 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/mach-sa1100/jornada720.c |
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* |
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* HP Jornada720 init code |
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* |
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* Copyright (C) 2007 Kristoffer Ericson <[email protected]> |
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* Copyright (C) 2006 Filip Zyzniewski <[email protected]> |
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* Copyright (C) 2005 Michael Gernoth <[email protected]> |
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*/ |
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#include <linux/init.h> |
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#include <linux/kernel.h> |
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#include <linux/tty.h> |
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#include <linux/delay.h> |
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#include <linux/gpio/machine.h> |
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#include <linux/platform_data/sa11x0-serial.h> |
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#include <linux/platform_device.h> |
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#include <linux/ioport.h> |
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#include <linux/mtd/mtd.h> |
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#include <linux/mtd/partitions.h> |
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#include <video/s1d13xxxfb.h> |
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#include <asm/hardware/sa1111.h> |
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#include <asm/page.h> |
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#include <asm/mach-types.h> |
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#include <asm/setup.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/flash.h> |
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#include <asm/mach/map.h> |
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#include <mach/hardware.h> |
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#include <mach/irqs.h> |
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#include "generic.h" |
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/* |
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* HP Documentation referred in this file: |
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* http://www.jlime.com/downloads/development/docs/jornada7xx/jornada720.txt |
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*/ |
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/* line 110 of HP's doc */ |
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#define TUCR_VAL 0x20000400 |
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/* memory space (line 52 of HP's doc) */ |
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#define SA1111REGSTART 0x40000000 |
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#define SA1111REGLEN 0x00002000 |
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#define EPSONREGSTART 0x48000000 |
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#define EPSONREGLEN 0x00100000 |
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#define EPSONFBSTART 0x48200000 |
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/* 512kB framebuffer */ |
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#define EPSONFBLEN 512*1024 |
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static struct s1d13xxxfb_regval s1d13xxxfb_initregs[] = { |
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/* line 344 of HP's doc */ |
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{0x0001,0x00}, // Miscellaneous Register |
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{0x01FC,0x00}, // Display Mode Register |
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{0x0004,0x00}, // General IO Pins Configuration Register 0 |
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{0x0005,0x00}, // General IO Pins Configuration Register 1 |
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{0x0008,0x00}, // General IO Pins Control Register 0 |
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{0x0009,0x00}, // General IO Pins Control Register 1 |
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{0x0010,0x01}, // Memory Clock Configuration Register |
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{0x0014,0x11}, // LCD Pixel Clock Configuration Register |
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{0x0018,0x01}, // CRT/TV Pixel Clock Configuration Register |
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{0x001C,0x01}, // MediaPlug Clock Configuration Register |
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{0x001E,0x01}, // CPU To Memory Wait State Select Register |
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{0x0020,0x00}, // Memory Configuration Register |
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{0x0021,0x45}, // DRAM Refresh Rate Register |
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{0x002A,0x01}, // DRAM Timings Control Register 0 |
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{0x002B,0x03}, // DRAM Timings Control Register 1 |
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{0x0030,0x1c}, // Panel Type Register |
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{0x0031,0x00}, // MOD Rate Register |
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{0x0032,0x4F}, // LCD Horizontal Display Width Register |
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{0x0034,0x07}, // LCD Horizontal Non-Display Period Register |
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{0x0035,0x01}, // TFT FPLINE Start Position Register |
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{0x0036,0x0B}, // TFT FPLINE Pulse Width Register |
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{0x0038,0xEF}, // LCD Vertical Display Height Register 0 |
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{0x0039,0x00}, // LCD Vertical Display Height Register 1 |
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{0x003A,0x13}, // LCD Vertical Non-Display Period Register |
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{0x003B,0x0B}, // TFT FPFRAME Start Position Register |
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{0x003C,0x01}, // TFT FPFRAME Pulse Width Register |
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{0x0040,0x05}, // LCD Display Mode Register (2:4bpp,3:8bpp,5:16bpp) |
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{0x0041,0x00}, // LCD Miscellaneous Register |
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{0x0042,0x00}, // LCD Display Start Address Register 0 |
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{0x0043,0x00}, // LCD Display Start Address Register 1 |
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{0x0044,0x00}, // LCD Display Start Address Register 2 |
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{0x0046,0x80}, // LCD Memory Address Offset Register 0 |
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{0x0047,0x02}, // LCD Memory Address Offset Register 1 |
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{0x0048,0x00}, // LCD Pixel Panning Register |
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{0x004A,0x00}, // LCD Display FIFO High Threshold Control Register |
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{0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register |
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{0x0050,0x4F}, // CRT/TV Horizontal Display Width Register |
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{0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register |
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{0x0053,0x01}, // CRT/TV HRTC Start Position Register |
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{0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register |
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{0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0 |
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{0x0057,0x01}, // CRT/TV Vertical Display Height Register 1 |
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{0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register |
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{0x0059,0x09}, // CRT/TV VRTC Start Position Register |
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{0x005A,0x01}, // CRT/TV VRTC Pulse Width Register |
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{0x005B,0x10}, // TV Output Control Register |
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{0x0060,0x03}, // CRT/TV Display Mode Register (2:4bpp,3:8bpp,5:16bpp) |
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{0x0062,0x00}, // CRT/TV Display Start Address Register 0 |
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{0x0063,0x00}, // CRT/TV Display Start Address Register 1 |
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{0x0064,0x00}, // CRT/TV Display Start Address Register 2 |
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{0x0066,0x40}, // CRT/TV Memory Address Offset Register 0 |
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{0x0067,0x01}, // CRT/TV Memory Address Offset Register 1 |
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{0x0068,0x00}, // CRT/TV Pixel Panning Register |
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{0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register |
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{0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register |
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{0x0070,0x00}, // LCD Ink/Cursor Control Register |
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{0x0071,0x01}, // LCD Ink/Cursor Start Address Register |
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{0x0072,0x00}, // LCD Cursor X Position Register 0 |
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{0x0073,0x00}, // LCD Cursor X Position Register 1 |
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{0x0074,0x00}, // LCD Cursor Y Position Register 0 |
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{0x0075,0x00}, // LCD Cursor Y Position Register 1 |
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{0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register |
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{0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register |
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{0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register |
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{0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register |
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{0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register |
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{0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register |
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{0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register |
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{0x0080,0x00}, // CRT/TV Ink/Cursor Control Register |
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{0x0081,0x01}, // CRT/TV Ink/Cursor Start Address Register |
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{0x0082,0x00}, // CRT/TV Cursor X Position Register 0 |
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{0x0083,0x00}, // CRT/TV Cursor X Position Register 1 |
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{0x0084,0x00}, // CRT/TV Cursor Y Position Register 0 |
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{0x0085,0x00}, // CRT/TV Cursor Y Position Register 1 |
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{0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register |
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{0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register |
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{0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register |
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{0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register |
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{0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register |
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{0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register |
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{0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register |
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{0x0100,0x00}, // BitBlt Control Register 0 |
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{0x0101,0x00}, // BitBlt Control Register 1 |
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{0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register |
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{0x0103,0x00}, // BitBlt Operation Register |
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{0x0104,0x00}, // BitBlt Source Start Address Register 0 |
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{0x0105,0x00}, // BitBlt Source Start Address Register 1 |
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{0x0106,0x00}, // BitBlt Source Start Address Register 2 |
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{0x0108,0x00}, // BitBlt Destination Start Address Register 0 |
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{0x0109,0x00}, // BitBlt Destination Start Address Register 1 |
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{0x010A,0x00}, // BitBlt Destination Start Address Register 2 |
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{0x010C,0x00}, // BitBlt Memory Address Offset Register 0 |
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{0x010D,0x00}, // BitBlt Memory Address Offset Register 1 |
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{0x0110,0x00}, // BitBlt Width Register 0 |
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{0x0111,0x00}, // BitBlt Width Register 1 |
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{0x0112,0x00}, // BitBlt Height Register 0 |
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{0x0113,0x00}, // BitBlt Height Register 1 |
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{0x0114,0x00}, // BitBlt Background Color Register 0 |
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{0x0115,0x00}, // BitBlt Background Color Register 1 |
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{0x0118,0x00}, // BitBlt Foreground Color Register 0 |
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{0x0119,0x00}, // BitBlt Foreground Color Register 1 |
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{0x01E0,0x00}, // Look-Up Table Mode Register |
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{0x01E2,0x00}, // Look-Up Table Address Register |
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/* not sure, wouldn't like to mess with the driver */ |
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{0x01E4,0x00}, // Look-Up Table Data Register |
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/* jornada doc says 0x00, but I trust the driver */ |
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{0x01F0,0x10}, // Power Save Configuration Register |
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{0x01F1,0x00}, // Power Save Status Register |
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{0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register |
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{0x01FC,0x01}, // Display Mode Register(0x01:LCD, 0x02:CRT, 0x03:LCD&CRT) |
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}; |
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static struct s1d13xxxfb_pdata s1d13xxxfb_data = { |
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.initregs = s1d13xxxfb_initregs, |
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.initregssize = ARRAY_SIZE(s1d13xxxfb_initregs), |
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.platform_init_video = NULL |
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}; |
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static struct resource s1d13xxxfb_resources[] = { |
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[0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN), |
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[1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN), |
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}; |
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static struct platform_device s1d13xxxfb_device = { |
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.name = S1D_DEVICENAME, |
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.id = 0, |
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.dev = { |
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.platform_data = &s1d13xxxfb_data, |
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}, |
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.num_resources = ARRAY_SIZE(s1d13xxxfb_resources), |
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.resource = s1d13xxxfb_resources, |
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}; |
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static struct gpiod_lookup_table jornada_pcmcia_gpiod_table = { |
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.dev_id = "1800", |
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.table = { |
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GPIO_LOOKUP("sa1111", 0, "s0-power", GPIO_ACTIVE_HIGH), |
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GPIO_LOOKUP("sa1111", 1, "s1-power", GPIO_ACTIVE_HIGH), |
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GPIO_LOOKUP("sa1111", 2, "s0-3v", GPIO_ACTIVE_HIGH), |
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GPIO_LOOKUP("sa1111", 3, "s1-3v", GPIO_ACTIVE_HIGH), |
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{ }, |
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}, |
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}; |
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static struct resource sa1111_resources[] = { |
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[0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN), |
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[1] = DEFINE_RES_IRQ(IRQ_GPIO1), |
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}; |
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static struct sa1111_platform_data sa1111_info = { |
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.disable_devs = SA1111_DEVID_PS2_MSE, |
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}; |
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static u64 sa1111_dmamask = 0xffffffffUL; |
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static struct platform_device sa1111_device = { |
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.name = "sa1111", |
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.id = 0, |
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.dev = { |
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.dma_mask = &sa1111_dmamask, |
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.coherent_dma_mask = 0xffffffff, |
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.platform_data = &sa1111_info, |
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}, |
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.num_resources = ARRAY_SIZE(sa1111_resources), |
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.resource = sa1111_resources, |
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}; |
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static struct platform_device jornada_ssp_device = { |
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.name = "jornada_ssp", |
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.id = -1, |
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}; |
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static struct resource jornada_kbd_resources[] = { |
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DEFINE_RES_IRQ(IRQ_GPIO0), |
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}; |
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static struct platform_device jornada_kbd_device = { |
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.name = "jornada720_kbd", |
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.id = -1, |
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.num_resources = ARRAY_SIZE(jornada_kbd_resources), |
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.resource = jornada_kbd_resources, |
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}; |
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static struct gpiod_lookup_table jornada_ts_gpiod_table = { |
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.dev_id = "jornada_ts", |
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.table = { |
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GPIO_LOOKUP("gpio", 9, "penup", GPIO_ACTIVE_HIGH), |
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}, |
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}; |
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static struct platform_device jornada_ts_device = { |
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.name = "jornada_ts", |
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.id = -1, |
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}; |
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static struct platform_device *devices[] __initdata = { |
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&sa1111_device, |
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&jornada_ssp_device, |
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&s1d13xxxfb_device, |
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&jornada_kbd_device, |
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&jornada_ts_device, |
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}; |
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static int __init jornada720_init(void) |
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{ |
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int ret = -ENODEV; |
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if (machine_is_jornada720()) { |
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/* we want to use gpio20 as input to drive the clock of our uart 3 */ |
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GPDR |= GPIO_GPIO20; /* Clear gpio20 pin as input */ |
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TUCR = TUCR_VAL; |
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GPSR = GPIO_GPIO20; /* start gpio20 pin */ |
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udelay(1); |
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GPCR = GPIO_GPIO20; /* stop gpio20 */ |
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udelay(1); |
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GPSR = GPIO_GPIO20; /* restart gpio20 */ |
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udelay(20); /* give it some time to restart */ |
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gpiod_add_lookup_table(&jornada_ts_gpiod_table); |
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gpiod_add_lookup_table(&jornada_pcmcia_gpiod_table); |
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ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
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} |
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return ret; |
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} |
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arch_initcall(jornada720_init); |
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static struct map_desc jornada720_io_desc[] __initdata = { |
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{ /* Epson registers */ |
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.virtual = 0xf0000000, |
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.pfn = __phys_to_pfn(EPSONREGSTART), |
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.length = EPSONREGLEN, |
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.type = MT_DEVICE |
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}, { /* Epson frame buffer */ |
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.virtual = 0xf1000000, |
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.pfn = __phys_to_pfn(EPSONFBSTART), |
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.length = EPSONFBLEN, |
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.type = MT_DEVICE |
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} |
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}; |
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static void __init jornada720_map_io(void) |
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{ |
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sa1100_map_io(); |
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iotable_init(jornada720_io_desc, ARRAY_SIZE(jornada720_io_desc)); |
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sa1100_register_uart(0, 3); |
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sa1100_register_uart(1, 1); |
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} |
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static struct mtd_partition jornada720_partitions[] = { |
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{ |
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.name = "JORNADA720 boot firmware", |
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.size = 0x00040000, |
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.offset = 0, |
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.mask_flags = MTD_WRITEABLE, /* force read-only */ |
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}, { |
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.name = "JORNADA720 kernel", |
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.size = 0x000c0000, |
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.offset = 0x00040000, |
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}, { |
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.name = "JORNADA720 params", |
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.size = 0x00040000, |
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.offset = 0x00100000, |
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}, { |
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.name = "JORNADA720 initrd", |
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.size = 0x00100000, |
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.offset = 0x00140000, |
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}, { |
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.name = "JORNADA720 root cramfs", |
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.size = 0x00300000, |
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.offset = 0x00240000, |
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}, { |
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.name = "JORNADA720 usr cramfs", |
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.size = 0x00800000, |
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.offset = 0x00540000, |
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}, { |
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.name = "JORNADA720 usr local", |
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.size = 0, /* will expand to the end of the flash */ |
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.offset = 0x00d00000, |
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} |
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}; |
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static void jornada720_set_vpp(int vpp) |
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{ |
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if (vpp) |
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/* enabling flash write (line 470 of HP's doc) */ |
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PPSR |= PPC_LDD7; |
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else |
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/* disabling flash write (line 470 of HP's doc) */ |
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PPSR &= ~PPC_LDD7; |
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PPDR |= PPC_LDD7; |
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} |
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static struct flash_platform_data jornada720_flash_data = { |
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.map_name = "cfi_probe", |
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.set_vpp = jornada720_set_vpp, |
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.parts = jornada720_partitions, |
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.nr_parts = ARRAY_SIZE(jornada720_partitions), |
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}; |
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static struct resource jornada720_flash_resource = |
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DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); |
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static void __init jornada720_mach_init(void) |
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{ |
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sa11x0_register_mtd(&jornada720_flash_data, &jornada720_flash_resource, 1); |
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} |
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MACHINE_START(JORNADA720, "HP Jornada 720") |
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/* Maintainer: Kristoffer Ericson <[email protected]> */ |
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.atag_offset = 0x100, |
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.map_io = jornada720_map_io, |
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.nr_irqs = SA1100_NR_IRQS, |
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.init_irq = sa1100_init_irq, |
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.init_time = sa1100_timer_init, |
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.init_machine = jornada720_mach_init, |
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.init_late = sa11x0_init_late, |
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#ifdef CONFIG_SA1111 |
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.dma_zone_size = SZ_1M, |
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#endif |
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.restart = sa11x0_restart, |
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MACHINE_END
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