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101 lines
3.1 KiB
101 lines
3.1 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* arch/arm/mach-sa1100/include/mach/irqs.h |
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* |
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* Copyright (C) 1996 Russell King |
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* Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus). |
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* Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation) |
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* |
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* 2001/11/14 RMK Cleaned up and standardised a lot of the IRQs. |
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*/ |
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#define IRQ_GPIO0_SC 1 |
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#define IRQ_GPIO1_SC 2 |
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#define IRQ_GPIO2_SC 3 |
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#define IRQ_GPIO3_SC 4 |
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#define IRQ_GPIO4_SC 5 |
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#define IRQ_GPIO5_SC 6 |
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#define IRQ_GPIO6_SC 7 |
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#define IRQ_GPIO7_SC 8 |
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#define IRQ_GPIO8_SC 9 |
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#define IRQ_GPIO9_SC 10 |
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#define IRQ_GPIO10_SC 11 |
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#define IRQ_GPIO11_27 12 |
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#define IRQ_LCD 13 /* LCD controller */ |
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#define IRQ_Ser0UDC 14 /* Ser. port 0 UDC */ |
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#define IRQ_Ser1SDLC 15 /* Ser. port 1 SDLC */ |
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#define IRQ_Ser1UART 16 /* Ser. port 1 UART */ |
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#define IRQ_Ser2ICP 17 /* Ser. port 2 ICP */ |
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#define IRQ_Ser3UART 18 /* Ser. port 3 UART */ |
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#define IRQ_Ser4MCP 19 /* Ser. port 4 MCP */ |
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#define IRQ_Ser4SSP 20 /* Ser. port 4 SSP */ |
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#define IRQ_DMA0 21 /* DMA controller channel 0 */ |
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#define IRQ_DMA1 22 /* DMA controller channel 1 */ |
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#define IRQ_DMA2 23 /* DMA controller channel 2 */ |
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#define IRQ_DMA3 24 /* DMA controller channel 3 */ |
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#define IRQ_DMA4 25 /* DMA controller channel 4 */ |
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#define IRQ_DMA5 26 /* DMA controller channel 5 */ |
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#define IRQ_OST0 27 /* OS Timer match 0 */ |
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#define IRQ_OST1 28 /* OS Timer match 1 */ |
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#define IRQ_OST2 29 /* OS Timer match 2 */ |
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#define IRQ_OST3 30 /* OS Timer match 3 */ |
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#define IRQ_RTC1Hz 31 /* RTC 1 Hz clock */ |
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#define IRQ_RTCAlrm 32 /* RTC Alarm */ |
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#define IRQ_GPIO0 33 |
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#define IRQ_GPIO1 34 |
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#define IRQ_GPIO2 35 |
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#define IRQ_GPIO3 36 |
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#define IRQ_GPIO4 37 |
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#define IRQ_GPIO5 38 |
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#define IRQ_GPIO6 39 |
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#define IRQ_GPIO7 40 |
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#define IRQ_GPIO8 41 |
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#define IRQ_GPIO9 42 |
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#define IRQ_GPIO10 43 |
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#define IRQ_GPIO11 44 |
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#define IRQ_GPIO12 45 |
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#define IRQ_GPIO13 46 |
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#define IRQ_GPIO14 47 |
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#define IRQ_GPIO15 48 |
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#define IRQ_GPIO16 49 |
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#define IRQ_GPIO17 50 |
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#define IRQ_GPIO18 51 |
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#define IRQ_GPIO19 52 |
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#define IRQ_GPIO20 53 |
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#define IRQ_GPIO21 54 |
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#define IRQ_GPIO22 55 |
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#define IRQ_GPIO23 56 |
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#define IRQ_GPIO24 57 |
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#define IRQ_GPIO25 58 |
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#define IRQ_GPIO26 59 |
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#define IRQ_GPIO27 60 |
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/* |
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* The next 16 interrupts are for board specific purposes. Since |
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* the kernel can only run on one machine at a time, we can re-use |
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* these. If you need more, increase IRQ_BOARD_END, but keep it |
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* within sensible limits. IRQs 61 to 76 are available. |
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*/ |
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#define IRQ_BOARD_START 61 |
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#define IRQ_BOARD_END 77 |
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/* |
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* Figure out the MAX IRQ number. |
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* |
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* Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically |
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* allocate their IRQs above NR_IRQS. |
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* |
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* LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has |
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* to be included in the NR_IRQS calculation. |
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*/ |
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#ifdef CONFIG_SHARP_LOCOMO |
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#define NR_IRQS_LOCOMO 4 |
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#else |
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#define NR_IRQS_LOCOMO 0 |
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#endif |
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#ifndef NR_IRQS |
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#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) |
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#endif |
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#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO)
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