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510 lines
12 KiB
510 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* linux/arch/arm/mach-pxa/pxa3xx.c |
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* |
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* code specific to pxa3xx aka Monahans |
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* |
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* Copyright (C) 2006 Marvell International Ltd. |
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* |
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* 2007-09-02: eric miao <[email protected]> |
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* initial version |
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*/ |
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#include <linux/dmaengine.h> |
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#include <linux/dma/pxa-dma.h> |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/gpio-pxa.h> |
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#include <linux/pm.h> |
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#include <linux/platform_device.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/platform_data/i2c-pxa.h> |
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#include <linux/platform_data/mmp_dma.h> |
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#include <asm/mach/map.h> |
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#include <asm/suspend.h> |
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#include <mach/hardware.h> |
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#include <mach/pxa3xx-regs.h> |
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#include <mach/reset.h> |
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#include <linux/platform_data/usb-ohci-pxa27x.h> |
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#include "pm.h" |
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#include <mach/dma.h> |
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#include <mach/smemc.h> |
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#include <mach/irqs.h> |
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#include "generic.h" |
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#include "devices.h" |
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#define PECR_IE(n) ((1 << ((n) * 2)) << 28) |
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#define PECR_IS(n) ((1 << ((n) * 2)) << 29) |
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extern void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)); |
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/* |
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* NAND NFC: DFI bus arbitration subset |
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*/ |
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#define NDCR (*(volatile u32 __iomem*)(NAND_VIRT + 0)) |
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#define NDCR_ND_ARB_EN (1 << 12) |
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#define NDCR_ND_ARB_CNTL (1 << 19) |
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#ifdef CONFIG_PM |
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#define ISRAM_START 0x5c000000 |
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#define ISRAM_SIZE SZ_256K |
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static void __iomem *sram; |
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static unsigned long wakeup_src; |
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/* |
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* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic |
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* memory controller has to be reinitialised, so we place some code |
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* in the SRAM to perform this function. |
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* |
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* We disable FIQs across the standby - otherwise, we might receive a |
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* FIQ while the SDRAM is unavailable. |
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*/ |
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static void pxa3xx_cpu_standby(unsigned int pwrmode) |
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{ |
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void (*fn)(unsigned int) = (void __force *)(sram + 0x8000); |
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memcpy_toio(sram + 0x8000, pm_enter_standby_start, |
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pm_enter_standby_end - pm_enter_standby_start); |
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AD2D0SR = ~0; |
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AD2D1SR = ~0; |
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AD2D0ER = wakeup_src; |
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AD2D1ER = 0; |
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ASCR = ASCR; |
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ARSR = ARSR; |
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local_fiq_disable(); |
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fn(pwrmode); |
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local_fiq_enable(); |
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AD2D0ER = 0; |
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AD2D1ER = 0; |
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} |
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/* |
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* NOTE: currently, the OBM (OEM Boot Module) binary comes along with |
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* PXA3xx development kits assumes that the resuming process continues |
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* with the address stored within the first 4 bytes of SDRAM. The PSPR |
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* register is used privately by BootROM and OBM, and _must_ be set to |
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* 0x5c014000 for the moment. |
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*/ |
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static void pxa3xx_cpu_pm_suspend(void) |
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{ |
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volatile unsigned long *p = (volatile void *)0xc0000000; |
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unsigned long saved_data = *p; |
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#ifndef CONFIG_IWMMXT |
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u64 acc0; |
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asm volatile(".arch_extension xscale\n\t" |
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"mra %Q0, %R0, acc0" : "=r" (acc0)); |
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#endif |
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/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */ |
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CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM); |
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CKENB |= 1 << (CKEN_HSIO2 & 0x1f); |
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/* clear and setup wakeup source */ |
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AD3SR = ~0; |
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AD3ER = wakeup_src; |
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ASCR = ASCR; |
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ARSR = ARSR; |
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PCFR |= (1u << 13); /* L1_DIS */ |
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PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */ |
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PSPR = 0x5c014000; |
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/* overwrite with the resume address */ |
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*p = __pa_symbol(cpu_resume); |
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cpu_suspend(0, pxa3xx_finish_suspend); |
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*p = saved_data; |
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AD3ER = 0; |
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#ifndef CONFIG_IWMMXT |
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asm volatile(".arch_extension xscale\n\t" |
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"mar acc0, %Q0, %R0" : "=r" (acc0)); |
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#endif |
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} |
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static void pxa3xx_cpu_pm_enter(suspend_state_t state) |
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{ |
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/* |
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* Don't sleep if no wakeup sources are defined |
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*/ |
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if (wakeup_src == 0) { |
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printk(KERN_ERR "Not suspending: no wakeup sources\n"); |
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return; |
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} |
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switch (state) { |
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case PM_SUSPEND_STANDBY: |
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pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2); |
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break; |
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case PM_SUSPEND_MEM: |
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pxa3xx_cpu_pm_suspend(); |
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break; |
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} |
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} |
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static int pxa3xx_cpu_pm_valid(suspend_state_t state) |
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{ |
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY; |
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} |
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static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = { |
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.valid = pxa3xx_cpu_pm_valid, |
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.enter = pxa3xx_cpu_pm_enter, |
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}; |
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static void __init pxa3xx_init_pm(void) |
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{ |
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sram = ioremap(ISRAM_START, ISRAM_SIZE); |
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if (!sram) { |
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printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n"); |
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return; |
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} |
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/* |
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* Since we copy wakeup code into the SRAM, we need to ensure |
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* that it is preserved over the low power modes. Note: bit 8 |
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* is undocumented in the developer manual, but must be set. |
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*/ |
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AD1R |= ADXR_L2 | ADXR_R0; |
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AD2R |= ADXR_L2 | ADXR_R0; |
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AD3R |= ADXR_L2 | ADXR_R0; |
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/* |
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* Clear the resume enable registers. |
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*/ |
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AD1D0ER = 0; |
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AD2D0ER = 0; |
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AD2D1ER = 0; |
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AD3ER = 0; |
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pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns; |
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} |
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static int pxa3xx_set_wake(struct irq_data *d, unsigned int on) |
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{ |
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unsigned long flags, mask = 0; |
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switch (d->irq) { |
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case IRQ_SSP3: |
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mask = ADXER_MFP_WSSP3; |
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break; |
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case IRQ_MSL: |
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mask = ADXER_WMSL0; |
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break; |
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case IRQ_USBH2: |
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case IRQ_USBH1: |
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mask = ADXER_WUSBH; |
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break; |
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case IRQ_KEYPAD: |
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mask = ADXER_WKP; |
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break; |
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case IRQ_AC97: |
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mask = ADXER_MFP_WAC97; |
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break; |
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case IRQ_USIM: |
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mask = ADXER_WUSIM0; |
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break; |
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case IRQ_SSP2: |
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mask = ADXER_MFP_WSSP2; |
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break; |
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case IRQ_I2C: |
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mask = ADXER_MFP_WI2C; |
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break; |
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case IRQ_STUART: |
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mask = ADXER_MFP_WUART3; |
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break; |
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case IRQ_BTUART: |
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mask = ADXER_MFP_WUART2; |
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break; |
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case IRQ_FFUART: |
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mask = ADXER_MFP_WUART1; |
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break; |
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case IRQ_MMC: |
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mask = ADXER_MFP_WMMC1; |
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break; |
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case IRQ_SSP: |
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mask = ADXER_MFP_WSSP1; |
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break; |
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case IRQ_RTCAlrm: |
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mask = ADXER_WRTC; |
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break; |
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case IRQ_SSP4: |
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mask = ADXER_MFP_WSSP4; |
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break; |
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case IRQ_TSI: |
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mask = ADXER_WTSI; |
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break; |
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case IRQ_USIM2: |
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mask = ADXER_WUSIM1; |
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break; |
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case IRQ_MMC2: |
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mask = ADXER_MFP_WMMC2; |
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break; |
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case IRQ_NAND: |
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mask = ADXER_MFP_WFLASH; |
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break; |
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case IRQ_USB2: |
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mask = ADXER_WUSB2; |
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break; |
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case IRQ_WAKEUP0: |
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mask = ADXER_WEXTWAKE0; |
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break; |
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case IRQ_WAKEUP1: |
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mask = ADXER_WEXTWAKE1; |
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break; |
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case IRQ_MMC3: |
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mask = ADXER_MFP_GEN12; |
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break; |
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default: |
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return -EINVAL; |
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} |
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local_irq_save(flags); |
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if (on) |
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wakeup_src |= mask; |
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else |
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wakeup_src &= ~mask; |
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local_irq_restore(flags); |
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return 0; |
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} |
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#else |
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static inline void pxa3xx_init_pm(void) {} |
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#define pxa3xx_set_wake NULL |
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#endif |
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static void pxa_ack_ext_wakeup(struct irq_data *d) |
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{ |
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PECR |= PECR_IS(d->irq - IRQ_WAKEUP0); |
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} |
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static void pxa_mask_ext_wakeup(struct irq_data *d) |
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{ |
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pxa_mask_irq(d); |
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PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0); |
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} |
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static void pxa_unmask_ext_wakeup(struct irq_data *d) |
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{ |
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pxa_unmask_irq(d); |
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PECR |= PECR_IE(d->irq - IRQ_WAKEUP0); |
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} |
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static int pxa_set_ext_wakeup_type(struct irq_data *d, unsigned int flow_type) |
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{ |
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if (flow_type & IRQ_TYPE_EDGE_RISING) |
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PWER |= 1 << (d->irq - IRQ_WAKEUP0); |
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if (flow_type & IRQ_TYPE_EDGE_FALLING) |
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PWER |= 1 << (d->irq - IRQ_WAKEUP0 + 2); |
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return 0; |
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} |
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static struct irq_chip pxa_ext_wakeup_chip = { |
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.name = "WAKEUP", |
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.irq_ack = pxa_ack_ext_wakeup, |
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.irq_mask = pxa_mask_ext_wakeup, |
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.irq_unmask = pxa_unmask_ext_wakeup, |
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.irq_set_type = pxa_set_ext_wakeup_type, |
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}; |
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static void __init pxa_init_ext_wakeup_irq(int (*fn)(struct irq_data *, |
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unsigned int)) |
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{ |
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int irq; |
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for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { |
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irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip, |
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handle_edge_irq); |
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irq_clear_status_flags(irq, IRQ_NOREQUEST); |
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} |
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pxa_ext_wakeup_chip.irq_set_wake = fn; |
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} |
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static void __init __pxa3xx_init_irq(void) |
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{ |
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/* enable CP6 access */ |
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u32 value; |
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__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value)); |
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value |= (1 << 6); |
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__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value)); |
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pxa_init_ext_wakeup_irq(pxa3xx_set_wake); |
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} |
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void __init pxa3xx_init_irq(void) |
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{ |
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__pxa3xx_init_irq(); |
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pxa_init_irq(56, pxa3xx_set_wake); |
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} |
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#ifdef CONFIG_OF |
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static int __init __init |
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pxa3xx_dt_init_irq(struct device_node *node, struct device_node *parent) |
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{ |
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__pxa3xx_init_irq(); |
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pxa_dt_irq_init(pxa3xx_set_wake); |
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set_handle_irq(ichp_handle_irq); |
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return 0; |
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} |
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IRQCHIP_DECLARE(pxa3xx_intc, "marvell,pxa-intc", pxa3xx_dt_init_irq); |
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#endif /* CONFIG_OF */ |
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static struct map_desc pxa3xx_io_desc[] __initdata = { |
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{ /* Mem Ctl */ |
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.virtual = (unsigned long)SMEMC_VIRT, |
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.pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), |
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.length = SMEMC_SIZE, |
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.type = MT_DEVICE |
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}, { |
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.virtual = (unsigned long)NAND_VIRT, |
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.pfn = __phys_to_pfn(NAND_PHYS), |
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.length = NAND_SIZE, |
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.type = MT_DEVICE |
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}, |
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}; |
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void __init pxa3xx_map_io(void) |
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{ |
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pxa_map_io(); |
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iotable_init(ARRAY_AND_SIZE(pxa3xx_io_desc)); |
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pxa3xx_get_clk_frequency_khz(1); |
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} |
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/* |
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* device registration specific to PXA3xx. |
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*/ |
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void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info) |
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{ |
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pxa_register_device(&pxa3xx_device_i2c_power, info); |
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} |
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static struct pxa_gpio_platform_data pxa3xx_gpio_pdata = { |
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.irq_base = PXA_GPIO_TO_IRQ(0), |
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}; |
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static struct platform_device *devices[] __initdata = { |
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&pxa27x_device_udc, |
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&pxa_device_pmu, |
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&pxa_device_i2s, |
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&pxa_device_asoc_ssp1, |
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&pxa_device_asoc_ssp2, |
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&pxa_device_asoc_ssp3, |
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&pxa_device_asoc_ssp4, |
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&pxa_device_asoc_platform, |
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&pxa_device_rtc, |
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&pxa3xx_device_ssp1, |
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&pxa3xx_device_ssp2, |
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&pxa3xx_device_ssp3, |
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&pxa3xx_device_ssp4, |
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&pxa27x_device_pwm0, |
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&pxa27x_device_pwm1, |
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}; |
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static const struct dma_slave_map pxa3xx_slave_map[] = { |
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/* PXA25x, PXA27x and PXA3xx common entries */ |
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{ "pxa2xx-ac97", "pcm_pcm_mic_mono", PDMA_FILTER_PARAM(LOWEST, 8) }, |
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{ "pxa2xx-ac97", "pcm_pcm_aux_mono_in", PDMA_FILTER_PARAM(LOWEST, 9) }, |
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{ "pxa2xx-ac97", "pcm_pcm_aux_mono_out", |
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PDMA_FILTER_PARAM(LOWEST, 10) }, |
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{ "pxa2xx-ac97", "pcm_pcm_stereo_in", PDMA_FILTER_PARAM(LOWEST, 11) }, |
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{ "pxa2xx-ac97", "pcm_pcm_stereo_out", PDMA_FILTER_PARAM(LOWEST, 12) }, |
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{ "pxa-ssp-dai.0", "rx", PDMA_FILTER_PARAM(LOWEST, 13) }, |
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{ "pxa-ssp-dai.0", "tx", PDMA_FILTER_PARAM(LOWEST, 14) }, |
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{ "pxa-ssp-dai.1", "rx", PDMA_FILTER_PARAM(LOWEST, 15) }, |
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{ "pxa-ssp-dai.1", "tx", PDMA_FILTER_PARAM(LOWEST, 16) }, |
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{ "pxa2xx-ir", "rx", PDMA_FILTER_PARAM(LOWEST, 17) }, |
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{ "pxa2xx-ir", "tx", PDMA_FILTER_PARAM(LOWEST, 18) }, |
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{ "pxa2xx-mci.0", "rx", PDMA_FILTER_PARAM(LOWEST, 21) }, |
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{ "pxa2xx-mci.0", "tx", PDMA_FILTER_PARAM(LOWEST, 22) }, |
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{ "pxa-ssp-dai.2", "rx", PDMA_FILTER_PARAM(LOWEST, 66) }, |
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{ "pxa-ssp-dai.2", "tx", PDMA_FILTER_PARAM(LOWEST, 67) }, |
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/* PXA3xx specific map */ |
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{ "pxa-ssp-dai.3", "rx", PDMA_FILTER_PARAM(LOWEST, 2) }, |
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{ "pxa-ssp-dai.3", "tx", PDMA_FILTER_PARAM(LOWEST, 3) }, |
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{ "pxa2xx-mci.1", "rx", PDMA_FILTER_PARAM(LOWEST, 93) }, |
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{ "pxa2xx-mci.1", "tx", PDMA_FILTER_PARAM(LOWEST, 94) }, |
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{ "pxa3xx-nand", "data", PDMA_FILTER_PARAM(LOWEST, 97) }, |
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{ "pxa2xx-mci.2", "rx", PDMA_FILTER_PARAM(LOWEST, 100) }, |
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{ "pxa2xx-mci.2", "tx", PDMA_FILTER_PARAM(LOWEST, 101) }, |
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}; |
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static struct mmp_dma_platdata pxa3xx_dma_pdata = { |
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.dma_channels = 32, |
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.nb_requestors = 100, |
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.slave_map = pxa3xx_slave_map, |
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.slave_map_cnt = ARRAY_SIZE(pxa3xx_slave_map), |
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}; |
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static int __init pxa3xx_init(void) |
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{ |
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int ret = 0; |
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if (cpu_is_pxa3xx()) { |
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reset_status = ARSR; |
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/* |
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* clear RDH bit every time after reset |
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* |
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* Note: the last 3 bits DxS are write-1-to-clear so carefully |
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* preserve them here in case they will be referenced later |
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*/ |
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ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S); |
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/* |
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* Disable DFI bus arbitration, to prevent a system bus lock if |
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* somebody disables the NAND clock (unused clock) while this |
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* bit remains set. |
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*/ |
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NDCR = (NDCR & ~NDCR_ND_ARB_EN) | NDCR_ND_ARB_CNTL; |
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pxa3xx_init_pm(); |
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enable_irq_wake(IRQ_WAKEUP0); |
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if (cpu_is_pxa320()) |
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enable_irq_wake(IRQ_WAKEUP1); |
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register_syscore_ops(&pxa_irq_syscore_ops); |
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register_syscore_ops(&pxa3xx_mfp_syscore_ops); |
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if (of_have_populated_dt()) |
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return 0; |
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pxa2xx_set_dmac_info(&pxa3xx_dma_pdata); |
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ret = platform_add_devices(devices, ARRAY_SIZE(devices)); |
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if (ret) |
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return ret; |
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if (cpu_is_pxa300() || cpu_is_pxa310() || cpu_is_pxa320()) { |
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platform_device_add_data(&pxa3xx_device_gpio, |
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&pxa3xx_gpio_pdata, |
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sizeof(pxa3xx_gpio_pdata)); |
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ret = platform_device_register(&pxa3xx_device_gpio); |
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} |
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} |
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return ret; |
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} |
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postcore_initcall(pxa3xx_init);
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