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80 lines
2.0 KiB
80 lines
2.0 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* GPIOs and interrupts for Palm Zire72 Handheld Computer |
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* |
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* Authors: Alex Osborne <[email protected]> |
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* Jan Herman <[email protected]> |
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* Sergey Lapin <[email protected]> |
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*/ |
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#ifndef _INCLUDE_PALMZ72_H_ |
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#define _INCLUDE_PALMZ72_H_ |
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/* Power and control */ |
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#define GPIO_NR_PALMZ72_GPIO_RESET 1 |
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#define GPIO_NR_PALMZ72_POWER_DETECT 0 |
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/* SD/MMC */ |
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#define GPIO_NR_PALMZ72_SD_DETECT_N 14 |
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#define GPIO_NR_PALMZ72_SD_POWER_N 98 |
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#define GPIO_NR_PALMZ72_SD_RO 115 |
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/* Touchscreen */ |
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#define GPIO_NR_PALMZ72_WM9712_IRQ 27 |
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/* IRDA - disable GPIO connected to SD pin of tranceiver (TFBS4710?) ? */ |
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#define GPIO_NR_PALMZ72_IR_DISABLE 49 |
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/* USB */ |
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#define GPIO_NR_PALMZ72_USB_DETECT_N 15 |
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#define GPIO_NR_PALMZ72_USB_PULLUP 95 |
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/* LCD/Backlight */ |
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#define GPIO_NR_PALMZ72_BL_POWER 20 |
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#define GPIO_NR_PALMZ72_LCD_POWER 96 |
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/* LED */ |
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#define GPIO_NR_PALMZ72_LED_GREEN 88 |
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/* Bluetooth */ |
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#define GPIO_NR_PALMZ72_BT_POWER 17 |
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#define GPIO_NR_PALMZ72_BT_RESET 83 |
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/* Camera */ |
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#define GPIO_NR_PALMZ72_CAM_PWDN 56 |
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#define GPIO_NR_PALMZ72_CAM_RESET 57 |
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#define GPIO_NR_PALMZ72_CAM_POWER 91 |
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/** Initial values **/ |
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/* Battery */ |
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#define PALMZ72_BAT_MAX_VOLTAGE 4000 /* 4.00v current voltage */ |
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#define PALMZ72_BAT_MIN_VOLTAGE 3550 /* 3.55v critical voltage */ |
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#define PALMZ72_BAT_MAX_CURRENT 0 /* unknown */ |
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#define PALMZ72_BAT_MIN_CURRENT 0 /* unknown */ |
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#define PALMZ72_BAT_MAX_CHARGE 1 /* unknown */ |
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#define PALMZ72_BAT_MIN_CHARGE 1 /* unknown */ |
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#define PALMZ72_MAX_LIFE_MINS 360 /* on-life in minutes */ |
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/* Backlight */ |
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#define PALMZ72_MAX_INTENSITY 0xFE |
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#define PALMZ72_DEFAULT_INTENSITY 0x7E |
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#define PALMZ72_LIMIT_MASK 0x7F |
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#define PALMZ72_PRESCALER 0x3F |
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#define PALMZ72_PERIOD_NS 3500 |
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#ifdef CONFIG_PM |
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struct palmz72_resume_info { |
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u32 magic0; /* 0x0 */ |
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u32 magic1; /* 0x4 */ |
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u32 resume_addr; /* 0x8 */ |
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u32 pad[11]; /* 0xc..0x37 */ |
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u32 arm_control; /* 0x38 */ |
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u32 aux_control; /* 0x3c */ |
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u32 ttb; /* 0x40 */ |
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u32 domain_access; /* 0x44 */ |
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u32 process_id; /* 0x48 */ |
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}; |
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#endif |
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#endif |
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