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379 lines
9.8 KiB
379 lines
9.8 KiB
/* |
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* arch/arm/mach-orion5x/db88f5281-setup.c |
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* |
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* Marvell Orion-2 Development Board Setup |
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* |
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* Maintainer: Tzachi Perelstein <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/gpio.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/pci.h> |
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#include <linux/irq.h> |
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#include <linux/mtd/physmap.h> |
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#include <linux/mtd/rawnand.h> |
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#include <linux/timer.h> |
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#include <linux/mv643xx_eth.h> |
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#include <linux/i2c.h> |
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#include <asm/mach-types.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/pci.h> |
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#include <linux/platform_data/mtd-orion_nand.h> |
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#include "common.h" |
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#include "mpp.h" |
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#include "orion5x.h" |
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/***************************************************************************** |
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* DB-88F5281 on board devices |
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****************************************************************************/ |
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/* |
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* 512K NOR flash Device bus boot chip select |
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*/ |
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#define DB88F5281_NOR_BOOT_BASE 0xf4000000 |
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#define DB88F5281_NOR_BOOT_SIZE SZ_512K |
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/* |
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* 7-Segment on Device bus chip select 0 |
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*/ |
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#define DB88F5281_7SEG_BASE 0xfa000000 |
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#define DB88F5281_7SEG_SIZE SZ_1K |
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/* |
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* 32M NOR flash on Device bus chip select 1 |
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*/ |
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#define DB88F5281_NOR_BASE 0xfc000000 |
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#define DB88F5281_NOR_SIZE SZ_32M |
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/* |
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* 32M NAND flash on Device bus chip select 2 |
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*/ |
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#define DB88F5281_NAND_BASE 0xfa800000 |
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#define DB88F5281_NAND_SIZE SZ_1K |
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/* |
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* PCI |
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*/ |
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#define DB88F5281_PCI_SLOT0_OFFS 7 |
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#define DB88F5281_PCI_SLOT0_IRQ_PIN 12 |
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#define DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN 13 |
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/***************************************************************************** |
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* 512M NOR Flash on Device bus Boot CS |
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****************************************************************************/ |
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static struct physmap_flash_data db88f5281_boot_flash_data = { |
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.width = 1, /* 8 bit bus width */ |
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}; |
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static struct resource db88f5281_boot_flash_resource = { |
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.flags = IORESOURCE_MEM, |
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.start = DB88F5281_NOR_BOOT_BASE, |
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.end = DB88F5281_NOR_BOOT_BASE + DB88F5281_NOR_BOOT_SIZE - 1, |
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}; |
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static struct platform_device db88f5281_boot_flash = { |
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.name = "physmap-flash", |
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.id = 0, |
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.dev = { |
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.platform_data = &db88f5281_boot_flash_data, |
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}, |
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.num_resources = 1, |
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.resource = &db88f5281_boot_flash_resource, |
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}; |
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/***************************************************************************** |
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* 32M NOR Flash on Device bus CS1 |
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****************************************************************************/ |
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static struct physmap_flash_data db88f5281_nor_flash_data = { |
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.width = 4, /* 32 bit bus width */ |
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}; |
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static struct resource db88f5281_nor_flash_resource = { |
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.flags = IORESOURCE_MEM, |
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.start = DB88F5281_NOR_BASE, |
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.end = DB88F5281_NOR_BASE + DB88F5281_NOR_SIZE - 1, |
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}; |
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static struct platform_device db88f5281_nor_flash = { |
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.name = "physmap-flash", |
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.id = 1, |
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.dev = { |
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.platform_data = &db88f5281_nor_flash_data, |
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}, |
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.num_resources = 1, |
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.resource = &db88f5281_nor_flash_resource, |
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}; |
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/***************************************************************************** |
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* 32M NAND Flash on Device bus CS2 |
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****************************************************************************/ |
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static struct mtd_partition db88f5281_nand_parts[] = { |
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{ |
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.name = "kernel", |
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.offset = 0, |
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.size = SZ_2M, |
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}, { |
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.name = "root", |
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.offset = SZ_2M, |
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.size = (SZ_16M - SZ_2M), |
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}, { |
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.name = "user", |
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.offset = SZ_16M, |
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.size = SZ_8M, |
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}, { |
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.name = "recovery", |
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.offset = (SZ_16M + SZ_8M), |
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.size = SZ_8M, |
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}, |
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}; |
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static struct resource db88f5281_nand_resource = { |
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.flags = IORESOURCE_MEM, |
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.start = DB88F5281_NAND_BASE, |
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.end = DB88F5281_NAND_BASE + DB88F5281_NAND_SIZE - 1, |
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}; |
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static struct orion_nand_data db88f5281_nand_data = { |
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.parts = db88f5281_nand_parts, |
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.nr_parts = ARRAY_SIZE(db88f5281_nand_parts), |
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.cle = 0, |
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.ale = 1, |
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.width = 8, |
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}; |
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static struct platform_device db88f5281_nand_flash = { |
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.name = "orion_nand", |
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.id = -1, |
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.dev = { |
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.platform_data = &db88f5281_nand_data, |
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}, |
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.resource = &db88f5281_nand_resource, |
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.num_resources = 1, |
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}; |
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/***************************************************************************** |
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* 7-Segment on Device bus CS0 |
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* Dummy counter every 2 sec |
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****************************************************************************/ |
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static void __iomem *db88f5281_7seg; |
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static struct timer_list db88f5281_timer; |
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static void db88f5281_7seg_event(struct timer_list *unused) |
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{ |
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static int count = 0; |
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writel(0, db88f5281_7seg + (count << 4)); |
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count = (count + 1) & 7; |
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mod_timer(&db88f5281_timer, jiffies + 2 * HZ); |
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} |
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static int __init db88f5281_7seg_init(void) |
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{ |
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if (machine_is_db88f5281()) { |
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db88f5281_7seg = ioremap(DB88F5281_7SEG_BASE, |
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DB88F5281_7SEG_SIZE); |
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if (!db88f5281_7seg) { |
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printk(KERN_ERR "Failed to ioremap db88f5281_7seg\n"); |
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return -EIO; |
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} |
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timer_setup(&db88f5281_timer, db88f5281_7seg_event, 0); |
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mod_timer(&db88f5281_timer, jiffies + 2 * HZ); |
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} |
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return 0; |
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} |
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__initcall(db88f5281_7seg_init); |
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/***************************************************************************** |
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* PCI |
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****************************************************************************/ |
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static void __init db88f5281_pci_preinit(void) |
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{ |
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int pin; |
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/* |
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* Configure PCI GPIO IRQ pins |
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*/ |
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pin = DB88F5281_PCI_SLOT0_IRQ_PIN; |
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if (gpio_request(pin, "PCI Int1") == 0) { |
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if (gpio_direction_input(pin) == 0) { |
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
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} else { |
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printk(KERN_ERR "db88f5281_pci_preinit failed to " |
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"set_irq_type pin %d\n", pin); |
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gpio_free(pin); |
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} |
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} else { |
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printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); |
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} |
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pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; |
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if (gpio_request(pin, "PCI Int2") == 0) { |
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if (gpio_direction_input(pin) == 0) { |
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irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); |
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} else { |
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printk(KERN_ERR "db88f5281_pci_preinit failed " |
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"to set_irq_type pin %d\n", pin); |
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gpio_free(pin); |
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} |
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} else { |
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printk(KERN_ERR "db88f5281_pci_preinit failed to gpio_request %d\n", pin); |
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} |
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} |
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static int __init db88f5281_pci_map_irq(const struct pci_dev *dev, u8 slot, |
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u8 pin) |
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{ |
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int irq; |
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/* |
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* Check for devices with hard-wired IRQs. |
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*/ |
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irq = orion5x_pci_map_irq(dev, slot, pin); |
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if (irq != -1) |
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return irq; |
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/* |
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* PCI IRQs are connected via GPIOs. |
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*/ |
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switch (slot - DB88F5281_PCI_SLOT0_OFFS) { |
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case 0: |
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return gpio_to_irq(DB88F5281_PCI_SLOT0_IRQ_PIN); |
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case 1: |
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case 2: |
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return gpio_to_irq(DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN); |
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default: |
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return -1; |
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} |
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} |
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static struct hw_pci db88f5281_pci __initdata = { |
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.nr_controllers = 2, |
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.preinit = db88f5281_pci_preinit, |
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.setup = orion5x_pci_sys_setup, |
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.scan = orion5x_pci_sys_scan_bus, |
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.map_irq = db88f5281_pci_map_irq, |
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}; |
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static int __init db88f5281_pci_init(void) |
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{ |
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if (machine_is_db88f5281()) |
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pci_common_init(&db88f5281_pci); |
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return 0; |
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} |
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subsys_initcall(db88f5281_pci_init); |
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/***************************************************************************** |
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* Ethernet |
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****************************************************************************/ |
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static struct mv643xx_eth_platform_data db88f5281_eth_data = { |
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.phy_addr = MV643XX_ETH_PHY_ADDR(8), |
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}; |
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/***************************************************************************** |
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* RTC DS1339 on I2C bus |
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****************************************************************************/ |
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static struct i2c_board_info __initdata db88f5281_i2c_rtc = { |
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I2C_BOARD_INFO("ds1339", 0x68), |
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}; |
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/***************************************************************************** |
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* General Setup |
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****************************************************************************/ |
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static unsigned int db88f5281_mpp_modes[] __initdata = { |
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MPP0_GPIO, /* USB Over Current */ |
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MPP1_GPIO, /* USB Vbat input */ |
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MPP2_PCI_ARB, /* PCI_REQn[2] */ |
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MPP3_PCI_ARB, /* PCI_GNTn[2] */ |
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MPP4_PCI_ARB, /* PCI_REQn[3] */ |
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MPP5_PCI_ARB, /* PCI_GNTn[3] */ |
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MPP6_GPIO, /* JP0, CON17.2 */ |
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MPP7_GPIO, /* JP1, CON17.1 */ |
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MPP8_GPIO, /* JP2, CON11.2 */ |
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MPP9_GPIO, /* JP3, CON11.3 */ |
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MPP10_GPIO, /* RTC int */ |
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MPP11_GPIO, /* Baud Rate Generator */ |
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MPP12_GPIO, /* PCI int 1 */ |
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MPP13_GPIO, /* PCI int 2 */ |
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MPP14_NAND, /* NAND_REn[2] */ |
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MPP15_NAND, /* NAND_WEn[2] */ |
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MPP16_UART, /* UART1_RX */ |
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MPP17_UART, /* UART1_TX */ |
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MPP18_UART, /* UART1_CTSn */ |
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MPP19_UART, /* UART1_RTSn */ |
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0, |
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}; |
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static void __init db88f5281_init(void) |
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{ |
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/* |
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* Basic Orion setup. Need to be called early. |
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*/ |
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orion5x_init(); |
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orion5x_mpp_conf(db88f5281_mpp_modes); |
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writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */ |
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/* |
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* Configure peripherals. |
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*/ |
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orion5x_ehci0_init(); |
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orion5x_eth_init(&db88f5281_eth_data); |
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orion5x_i2c_init(); |
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orion5x_uart0_init(); |
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orion5x_uart1_init(); |
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET, |
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ORION_MBUS_DEVBUS_BOOT_ATTR, |
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DB88F5281_NOR_BOOT_BASE, |
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DB88F5281_NOR_BOOT_SIZE); |
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platform_device_register(&db88f5281_boot_flash); |
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0), |
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ORION_MBUS_DEVBUS_ATTR(0), |
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DB88F5281_7SEG_BASE, |
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DB88F5281_7SEG_SIZE); |
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1), |
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ORION_MBUS_DEVBUS_ATTR(1), |
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DB88F5281_NOR_BASE, |
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DB88F5281_NOR_SIZE); |
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platform_device_register(&db88f5281_nor_flash); |
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mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2), |
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ORION_MBUS_DEVBUS_ATTR(2), |
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DB88F5281_NAND_BASE, |
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DB88F5281_NAND_SIZE); |
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platform_device_register(&db88f5281_nand_flash); |
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i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); |
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} |
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MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") |
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/* Maintainer: Tzachi Perelstein <[email protected]> */ |
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.atag_offset = 0x100, |
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.nr_irqs = ORION5X_NR_IRQS, |
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.init_machine = db88f5281_init, |
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.map_io = orion5x_map_io, |
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.init_early = orion5x_init_early, |
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.init_irq = orion5x_init_irq, |
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.init_time = orion5x_timer_init, |
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.restart = orion5x_restart, |
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MACHINE_END
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