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898 lines
24 KiB
898 lines
24 KiB
/* |
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* OMAP Voltage Controller (VC) interface |
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* |
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* Copyright (C) 2011 Texas Instruments, Inc. |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/bug.h> |
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#include <linux/io.h> |
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|
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#include <asm/div64.h> |
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|
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#include "iomap.h" |
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#include "soc.h" |
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#include "voltage.h" |
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#include "vc.h" |
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#include "prm-regbits-34xx.h" |
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#include "prm-regbits-44xx.h" |
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#include "prm44xx.h" |
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#include "pm.h" |
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#include "scrm44xx.h" |
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#include "control.h" |
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#define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14) |
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#define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13) |
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#define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12) |
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#define OMAP4430_VDD_IVA_PRESENCE BIT(9) |
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#define OMAP4430_VDD_MPU_PRESENCE BIT(8) |
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#define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4) |
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#define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2) |
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#define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0) |
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#define OMAP4430_AUTO_CTRL_VDD_RET 2 |
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#define OMAP4430_VDD_I2C_DISABLE_MASK \ |
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(OMAP4430_VDD_IVA_I2C_DISABLE | \ |
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OMAP4430_VDD_MPU_I2C_DISABLE | \ |
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OMAP4430_VDD_CORE_I2C_DISABLE) |
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#define OMAP4_VDD_DEFAULT_VAL \ |
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(OMAP4430_VDD_I2C_DISABLE_MASK | \ |
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OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \ |
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OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \ |
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OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \ |
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OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET)) |
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#define OMAP4_VDD_RET_VAL \ |
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(OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK) |
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|
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/** |
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* struct omap_vc_channel_cfg - describe the cfg_channel bitfield |
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* @sa: bit for slave address |
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* @rav: bit for voltage configuration register |
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* @rac: bit for command configuration register |
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* @racen: enable bit for RAC |
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* @cmd: bit for command value set selection |
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* |
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* Channel configuration bits, common for OMAP3+ |
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* OMAP3 register: PRM_VC_CH_CONF |
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* OMAP4 register: PRM_VC_CFG_CHANNEL |
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* OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG |
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*/ |
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struct omap_vc_channel_cfg { |
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u8 sa; |
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u8 rav; |
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u8 rac; |
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u8 racen; |
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u8 cmd; |
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}; |
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static struct omap_vc_channel_cfg vc_default_channel_cfg = { |
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.sa = BIT(0), |
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.rav = BIT(1), |
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.rac = BIT(2), |
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.racen = BIT(3), |
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.cmd = BIT(4), |
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}; |
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/* |
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* On OMAP3+, all VC channels have the above default bitfield |
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* configuration, except the OMAP4 MPU channel. This appears |
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* to be a freak accident as every other VC channel has the |
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* default configuration, thus creating a mutant channel config. |
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*/ |
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static struct omap_vc_channel_cfg vc_mutant_channel_cfg = { |
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.sa = BIT(0), |
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.rav = BIT(2), |
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.rac = BIT(3), |
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.racen = BIT(4), |
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.cmd = BIT(1), |
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}; |
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static struct omap_vc_channel_cfg *vc_cfg_bits; |
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|
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/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */ |
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static u32 sr_i2c_pcb_length = 63; |
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#define CFG_CHANNEL_MASK 0x1f |
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|
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/** |
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* omap_vc_config_channel - configure VC channel to PMIC mappings |
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* @voltdm: pointer to voltagdomain defining the desired VC channel |
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* |
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* Configures the VC channel to PMIC mappings for the following |
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* PMIC settings |
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* - i2c slave address (SA) |
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* - voltage configuration address (RAV) |
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* - command configuration address (RAC) and enable bit (RACEN) |
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* - command values for ON, ONLP, RET and OFF (CMD) |
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* |
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* This function currently only allows flexible configuration of the |
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* non-default channel. Starting with OMAP4, there are more than 2 |
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* channels, with one defined as the default (on OMAP4, it's MPU.) |
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* Only the non-default channel can be configured. |
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*/ |
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static int omap_vc_config_channel(struct voltagedomain *voltdm) |
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{ |
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struct omap_vc_channel *vc = voltdm->vc; |
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|
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/* |
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* For default channel, the only configurable bit is RACEN. |
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* All others must stay at zero (see function comment above.) |
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*/ |
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if (vc->flags & OMAP_VC_CHANNEL_DEFAULT) |
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vc->cfg_channel &= vc_cfg_bits->racen; |
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voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift, |
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vc->cfg_channel << vc->cfg_channel_sa_shift, |
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vc->cfg_channel_reg); |
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return 0; |
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} |
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/* Voltage scale and accessory APIs */ |
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int omap_vc_pre_scale(struct voltagedomain *voltdm, |
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unsigned long target_volt, |
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u8 *target_vsel, u8 *current_vsel) |
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{ |
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struct omap_vc_channel *vc = voltdm->vc; |
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u32 vc_cmdval; |
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/* Check if sufficient pmic info is available for this vdd */ |
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if (!voltdm->pmic) { |
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pr_err("%s: Insufficient pmic info to scale the vdd_%s\n", |
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__func__, voltdm->name); |
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return -EINVAL; |
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} |
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if (!voltdm->pmic->uv_to_vsel) { |
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pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n", |
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__func__, voltdm->name); |
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return -ENODATA; |
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} |
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if (!voltdm->read || !voltdm->write) { |
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pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
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__func__, voltdm->name); |
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return -EINVAL; |
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} |
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*target_vsel = voltdm->pmic->uv_to_vsel(target_volt); |
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*current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt); |
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/* Setting the ON voltage to the new target voltage */ |
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vc_cmdval = voltdm->read(vc->cmdval_reg); |
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vc_cmdval &= ~vc->common->cmd_on_mask; |
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vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift); |
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voltdm->write(vc_cmdval, vc->cmdval_reg); |
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voltdm->vc_param->on = target_volt; |
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omap_vp_update_errorgain(voltdm, target_volt); |
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return 0; |
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} |
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void omap_vc_post_scale(struct voltagedomain *voltdm, |
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unsigned long target_volt, |
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u8 target_vsel, u8 current_vsel) |
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{ |
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u32 smps_steps = 0, smps_delay = 0; |
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smps_steps = abs(target_vsel - current_vsel); |
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/* SMPS slew rate / step size. 2us added as buffer. */ |
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smps_delay = ((smps_steps * voltdm->pmic->step_size) / |
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voltdm->pmic->slew_rate) + 2; |
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udelay(smps_delay); |
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} |
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/* vc_bypass_scale - VC bypass method of voltage scaling */ |
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int omap_vc_bypass_scale(struct voltagedomain *voltdm, |
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unsigned long target_volt) |
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{ |
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struct omap_vc_channel *vc = voltdm->vc; |
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u32 loop_cnt = 0, retries_cnt = 0; |
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u32 vc_valid, vc_bypass_val_reg, vc_bypass_value; |
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u8 target_vsel, current_vsel; |
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int ret; |
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ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, ¤t_vsel); |
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if (ret) |
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return ret; |
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vc_valid = vc->common->valid; |
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vc_bypass_val_reg = vc->common->bypass_val_reg; |
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vc_bypass_value = (target_vsel << vc->common->data_shift) | |
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(vc->volt_reg_addr << vc->common->regaddr_shift) | |
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(vc->i2c_slave_addr << vc->common->slaveaddr_shift); |
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voltdm->write(vc_bypass_value, vc_bypass_val_reg); |
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voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg); |
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vc_bypass_value = voltdm->read(vc_bypass_val_reg); |
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/* |
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* Loop till the bypass command is acknowledged from the SMPS. |
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* NOTE: This is legacy code. The loop count and retry count needs |
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* to be revisited. |
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*/ |
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while (!(vc_bypass_value & vc_valid)) { |
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loop_cnt++; |
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if (retries_cnt > 10) { |
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pr_warn("%s: Retry count exceeded\n", __func__); |
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return -ETIMEDOUT; |
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} |
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if (loop_cnt > 50) { |
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retries_cnt++; |
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loop_cnt = 0; |
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udelay(10); |
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} |
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vc_bypass_value = voltdm->read(vc_bypass_val_reg); |
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} |
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omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel); |
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return 0; |
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} |
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/* Convert microsecond value to number of 32kHz clock cycles */ |
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static inline u32 omap_usec_to_32k(u32 usec) |
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{ |
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return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL); |
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} |
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struct omap3_vc_timings { |
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u32 voltsetup1; |
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u32 voltsetup2; |
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}; |
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struct omap3_vc { |
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struct voltagedomain *vd; |
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u32 voltctrl; |
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u32 voltsetup1; |
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u32 voltsetup2; |
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struct omap3_vc_timings timings[2]; |
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}; |
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static struct omap3_vc vc; |
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void omap3_vc_set_pmic_signaling(int core_next_state) |
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{ |
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struct voltagedomain *vd = vc.vd; |
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struct omap3_vc_timings *c = vc.timings; |
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u32 voltctrl, voltsetup1, voltsetup2; |
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voltctrl = vc.voltctrl; |
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voltsetup1 = vc.voltsetup1; |
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voltsetup2 = vc.voltsetup2; |
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switch (core_next_state) { |
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case PWRDM_POWER_OFF: |
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voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET | |
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OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); |
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voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF; |
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if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF) |
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voltsetup2 = c->voltsetup2; |
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else |
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voltsetup1 = c->voltsetup1; |
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break; |
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case PWRDM_POWER_RET: |
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default: |
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c++; |
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voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF | |
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OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP); |
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voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET; |
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voltsetup1 = c->voltsetup1; |
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break; |
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} |
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if (voltctrl != vc.voltctrl) { |
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vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET); |
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vc.voltctrl = voltctrl; |
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} |
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if (voltsetup1 != vc.voltsetup1) { |
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vd->write(c->voltsetup1, |
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OMAP3_PRM_VOLTSETUP1_OFFSET); |
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vc.voltsetup1 = voltsetup1; |
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} |
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if (voltsetup2 != vc.voltsetup2) { |
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vd->write(c->voltsetup2, |
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OMAP3_PRM_VOLTSETUP2_OFFSET); |
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vc.voltsetup2 = voltsetup2; |
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} |
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} |
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void omap4_vc_set_pmic_signaling(int core_next_state) |
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{ |
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struct voltagedomain *vd = vc.vd; |
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u32 val; |
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if (!vd) |
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return; |
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switch (core_next_state) { |
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case PWRDM_POWER_RET: |
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val = OMAP4_VDD_RET_VAL; |
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break; |
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default: |
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val = OMAP4_VDD_DEFAULT_VAL; |
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break; |
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} |
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vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET); |
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} |
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/* |
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* Configure signal polarity for sys_clkreq and sys_off_mode pins |
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* as the default values are wrong and can cause the system to hang |
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* if any twl4030 scripts are loaded. |
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*/ |
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static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm) |
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{ |
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u32 val; |
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|
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if (vc.vd) |
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return; |
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vc.vd = voltdm; |
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val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET); |
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if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) || |
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(val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) { |
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val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL; |
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val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL; |
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pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n", |
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val); |
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voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET); |
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} |
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/* |
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* By default let's use I2C4 signaling for retention idle |
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* and sys_off_mode pin signaling for off idle. This way we |
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* have sys_clk_req pin go down for retention and both |
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* sys_clk_req and sys_off_mode pins will go down for off |
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* idle. And we can also scale voltages to zero for off-idle. |
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* Note that no actual voltage scaling during off-idle will |
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* happen unless the board specific twl4030 PMIC scripts are |
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* loaded. See also omap_vc_i2c_init for comments regarding |
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* erratum i531. |
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*/ |
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val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET); |
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if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) { |
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val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF; |
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pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n", |
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val); |
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voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET); |
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} |
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vc.voltctrl = val; |
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omap3_vc_set_pmic_signaling(PWRDM_POWER_ON); |
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} |
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static void omap3_init_voltsetup1(struct voltagedomain *voltdm, |
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struct omap3_vc_timings *c, u32 idle) |
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{ |
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unsigned long val; |
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|
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val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate; |
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val *= voltdm->sys_clk.rate / 8 / 1000000 + 1; |
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val <<= __ffs(voltdm->vfsm->voltsetup_mask); |
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c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask; |
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c->voltsetup1 |= val; |
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} |
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|
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/** |
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* omap3_set_i2c_timings - sets i2c sleep timings for a channel |
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* @voltdm: channel to configure |
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* @off_mode: select whether retention or off mode values used |
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* |
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* Calculates and sets up voltage controller to use I2C based |
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* voltage scaling for sleep modes. This can be used for either off mode |
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* or retention. Off mode has additionally an option to use sys_off_mode |
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* pad, which uses a global signal to program the whole power IC to |
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* off-mode. |
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* |
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* Note that pmic is not controlling the voltage scaling during |
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* retention signaled over I2C4, so we can keep voltsetup2 as 0. |
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* And the oscillator is not shut off over I2C4, so no need to |
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* set clksetup. |
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*/ |
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static void omap3_set_i2c_timings(struct voltagedomain *voltdm) |
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{ |
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struct omap3_vc_timings *c = vc.timings; |
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|
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/* Configure PRWDM_POWER_OFF over I2C4 */ |
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omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off); |
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c++; |
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/* Configure PRWDM_POWER_RET over I2C4 */ |
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omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret); |
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} |
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|
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/** |
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* omap3_set_off_timings - sets off-mode timings for a channel |
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* @voltdm: channel to configure |
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* |
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* Calculates and sets up off-mode timings for a channel. Off-mode |
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* can use either I2C based voltage scaling, or alternatively |
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* sys_off_mode pad can be used to send a global command to power IC.n, |
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* sys_off_mode has the additional benefit that voltages can be |
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* scaled to zero volt level with TWL4030 / TWL5030, I2C can only |
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* scale to 600mV. |
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* |
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* Note that omap is not controlling the voltage scaling during |
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* off idle signaled by sys_off_mode, so we can keep voltsetup1 |
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* as 0. |
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*/ |
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static void omap3_set_off_timings(struct voltagedomain *voltdm) |
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{ |
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struct omap3_vc_timings *c = vc.timings; |
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u32 tstart, tshut, clksetup, voltoffset; |
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|
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if (c->voltsetup2) |
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return; |
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omap_pm_get_oscillator(&tstart, &tshut); |
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if (tstart == ULONG_MAX) { |
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pr_debug("PM: oscillator start-up time not initialized, using 10ms\n"); |
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clksetup = omap_usec_to_32k(10000); |
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} else { |
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clksetup = omap_usec_to_32k(tstart); |
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} |
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|
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/* |
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* For twl4030 errata 27, we need to allow minimum ~488.32 us wait to |
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* switch from HFCLKIN to internal oscillator. That means timings |
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* have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And |
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* that means we can calculate the value based on the oscillator |
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* start-up time since voltoffset2 = clksetup - voltoffset. |
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*/ |
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voltoffset = omap_usec_to_32k(488); |
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c->voltsetup2 = clksetup - voltoffset; |
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voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET); |
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voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET); |
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} |
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|
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static void __init omap3_vc_init_channel(struct voltagedomain *voltdm) |
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{ |
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omap3_vc_init_pmic_signaling(voltdm); |
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omap3_set_off_timings(voltdm); |
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omap3_set_i2c_timings(voltdm); |
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} |
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|
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/** |
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* omap4_calc_volt_ramp - calculates voltage ramping delays on omap4 |
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* @voltdm: channel to calculate values for |
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* @voltage_diff: voltage difference in microvolts |
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* |
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* Calculates voltage ramp prescaler + counter values for a voltage |
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* difference on omap4. Returns a field value suitable for writing to |
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* VOLTSETUP register for a channel in following format: |
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* bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference. |
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*/ |
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static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff) |
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{ |
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u32 prescaler; |
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u32 cycles; |
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u32 time; |
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|
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time = voltage_diff / voltdm->pmic->slew_rate; |
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|
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cycles = voltdm->sys_clk.rate / 1000 * time / 1000; |
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|
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cycles /= 64; |
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prescaler = 0; |
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|
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/* shift to next prescaler until no overflow */ |
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|
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/* scale for div 256 = 64 * 4 */ |
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if (cycles > 63) { |
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cycles /= 4; |
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prescaler++; |
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} |
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|
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/* scale for div 512 = 256 * 2 */ |
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if (cycles > 63) { |
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cycles /= 2; |
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prescaler++; |
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} |
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|
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/* scale for div 2048 = 512 * 4 */ |
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if (cycles > 63) { |
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cycles /= 4; |
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prescaler++; |
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} |
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|
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/* check for overflow => invalid ramp time */ |
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if (cycles > 63) { |
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pr_warn("%s: invalid setuptime for vdd_%s\n", __func__, |
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voltdm->name); |
|
return 0; |
|
} |
|
|
|
cycles++; |
|
|
|
return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) | |
|
(cycles << OMAP4430_RAMP_UP_COUNT_SHIFT); |
|
} |
|
|
|
/** |
|
* omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield |
|
* @usec: microseconds |
|
* @shift: number of bits to shift left |
|
* @mask: bitfield mask |
|
* |
|
* Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is |
|
* shifted to requested position, and checked agains the mask value. |
|
* If larger, forced to the max value of the field (i.e. the mask itself.) |
|
* Returns the SCRM bitfield value. |
|
*/ |
|
static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask) |
|
{ |
|
u32 val; |
|
|
|
val = omap_usec_to_32k(usec) << shift; |
|
|
|
/* Check for overflow, if yes, force to max value */ |
|
if (val > mask) |
|
val = mask; |
|
|
|
return val; |
|
} |
|
|
|
/** |
|
* omap4_set_timings - set voltage ramp timings for a channel |
|
* @voltdm: channel to configure |
|
* @off_mode: whether off-mode values are used |
|
* |
|
* Calculates and sets the voltage ramp up / down values for a channel. |
|
*/ |
|
static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode) |
|
{ |
|
u32 val; |
|
u32 ramp; |
|
int offset; |
|
u32 tstart, tshut; |
|
|
|
if (off_mode) { |
|
ramp = omap4_calc_volt_ramp(voltdm, |
|
voltdm->vc_param->on - voltdm->vc_param->off); |
|
offset = voltdm->vfsm->voltsetup_off_reg; |
|
} else { |
|
ramp = omap4_calc_volt_ramp(voltdm, |
|
voltdm->vc_param->on - voltdm->vc_param->ret); |
|
offset = voltdm->vfsm->voltsetup_reg; |
|
} |
|
|
|
if (!ramp) |
|
return; |
|
|
|
val = voltdm->read(offset); |
|
|
|
val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT; |
|
|
|
val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT; |
|
|
|
voltdm->write(val, offset); |
|
|
|
omap_pm_get_oscillator(&tstart, &tshut); |
|
|
|
val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT, |
|
OMAP4_SETUPTIME_MASK); |
|
val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT, |
|
OMAP4_DOWNTIME_MASK); |
|
|
|
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); |
|
} |
|
|
|
static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm) |
|
{ |
|
if (vc.vd) |
|
return; |
|
|
|
vc.vd = voltdm; |
|
voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET); |
|
} |
|
|
|
/* OMAP4 specific voltage init functions */ |
|
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) |
|
{ |
|
omap4_vc_init_pmic_signaling(voltdm); |
|
omap4_set_timings(voltdm, true); |
|
omap4_set_timings(voltdm, false); |
|
} |
|
|
|
struct i2c_init_data { |
|
u8 loadbits; |
|
u8 load; |
|
u8 hsscll_38_4; |
|
u8 hsscll_26; |
|
u8 hsscll_19_2; |
|
u8 hsscll_16_8; |
|
u8 hsscll_12; |
|
}; |
|
|
|
static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = { |
|
{ |
|
.load = 50, |
|
.loadbits = 0x3, |
|
.hsscll_38_4 = 13, |
|
.hsscll_26 = 11, |
|
.hsscll_19_2 = 9, |
|
.hsscll_16_8 = 9, |
|
.hsscll_12 = 8, |
|
}, |
|
{ |
|
.load = 25, |
|
.loadbits = 0x2, |
|
.hsscll_38_4 = 13, |
|
.hsscll_26 = 11, |
|
.hsscll_19_2 = 9, |
|
.hsscll_16_8 = 9, |
|
.hsscll_12 = 8, |
|
}, |
|
{ |
|
.load = 12, |
|
.loadbits = 0x1, |
|
.hsscll_38_4 = 11, |
|
.hsscll_26 = 10, |
|
.hsscll_19_2 = 9, |
|
.hsscll_16_8 = 9, |
|
.hsscll_12 = 8, |
|
}, |
|
{ |
|
.load = 0, |
|
.loadbits = 0x0, |
|
.hsscll_38_4 = 12, |
|
.hsscll_26 = 10, |
|
.hsscll_19_2 = 9, |
|
.hsscll_16_8 = 8, |
|
.hsscll_12 = 8, |
|
}, |
|
}; |
|
|
|
/** |
|
* omap4_vc_i2c_timing_init - sets up board I2C timing parameters |
|
* @voltdm: voltagedomain pointer to get data from |
|
* |
|
* Use PMIC + board supplied settings for calculating the total I2C |
|
* channel capacitance and set the timing parameters based on this. |
|
* Pre-calculated values are provided in data tables, as it is not |
|
* too straightforward to calculate these runtime. |
|
*/ |
|
static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm) |
|
{ |
|
u32 capacitance; |
|
u32 val; |
|
u16 hsscll; |
|
const struct i2c_init_data *i2c_data; |
|
|
|
if (!voltdm->pmic->i2c_high_speed) { |
|
pr_info("%s: using bootloader low-speed timings\n", __func__); |
|
return; |
|
} |
|
|
|
/* PCB trace capacitance, 0.125pF / mm => mm / 8 */ |
|
capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8); |
|
|
|
/* OMAP pad capacitance */ |
|
capacitance += 4; |
|
|
|
/* PMIC pad capacitance */ |
|
capacitance += voltdm->pmic->i2c_pad_load; |
|
|
|
/* Search for capacitance match in the table */ |
|
i2c_data = omap4_i2c_timing_data; |
|
|
|
while (i2c_data->load > capacitance) |
|
i2c_data++; |
|
|
|
/* Select proper values based on sysclk frequency */ |
|
switch (voltdm->sys_clk.rate) { |
|
case 38400000: |
|
hsscll = i2c_data->hsscll_38_4; |
|
break; |
|
case 26000000: |
|
hsscll = i2c_data->hsscll_26; |
|
break; |
|
case 19200000: |
|
hsscll = i2c_data->hsscll_19_2; |
|
break; |
|
case 16800000: |
|
hsscll = i2c_data->hsscll_16_8; |
|
break; |
|
case 12000000: |
|
hsscll = i2c_data->hsscll_12; |
|
break; |
|
default: |
|
pr_warn("%s: unsupported sysclk rate: %d!\n", __func__, |
|
voltdm->sys_clk.rate); |
|
return; |
|
} |
|
|
|
/* Loadbits define pull setup for the I2C channels */ |
|
val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29; |
|
|
|
/* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */ |
|
writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + |
|
OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2)); |
|
|
|
/* HSSCLH can always be zero */ |
|
val = hsscll << OMAP4430_HSSCLL_SHIFT; |
|
val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT); |
|
|
|
/* Write setup times to I2C config register */ |
|
voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET); |
|
} |
|
|
|
|
|
|
|
/** |
|
* omap_vc_i2c_init - initialize I2C interface to PMIC |
|
* @voltdm: voltage domain containing VC data |
|
* |
|
* Use PMIC supplied settings for I2C high-speed mode and |
|
* master code (if set) and program the VC I2C configuration |
|
* register. |
|
* |
|
* The VC I2C configuration is common to all VC channels, |
|
* so this function only configures I2C for the first VC |
|
* channel registers. All other VC channels will use the |
|
* same configuration. |
|
*/ |
|
static void __init omap_vc_i2c_init(struct voltagedomain *voltdm) |
|
{ |
|
struct omap_vc_channel *vc = voltdm->vc; |
|
static bool initialized; |
|
static bool i2c_high_speed; |
|
u8 mcode; |
|
|
|
if (initialized) { |
|
if (voltdm->pmic->i2c_high_speed != i2c_high_speed) |
|
pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n", |
|
__func__, voltdm->name, i2c_high_speed); |
|
return; |
|
} |
|
|
|
/* |
|
* Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around |
|
* erratum i531 "Extra Power Consumed When Repeated Start Operation |
|
* Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)". |
|
* Otherwise I2C4 eventually leads into about 23mW extra power being |
|
* consumed even during off idle using VMODE. |
|
*/ |
|
i2c_high_speed = voltdm->pmic->i2c_high_speed; |
|
if (i2c_high_speed) |
|
voltdm->rmw(vc->common->i2c_cfg_clear_mask, |
|
vc->common->i2c_cfg_hsen_mask, |
|
vc->common->i2c_cfg_reg); |
|
|
|
mcode = voltdm->pmic->i2c_mcode; |
|
if (mcode) |
|
voltdm->rmw(vc->common->i2c_mcode_mask, |
|
mcode << __ffs(vc->common->i2c_mcode_mask), |
|
vc->common->i2c_cfg_reg); |
|
|
|
if (cpu_is_omap44xx()) |
|
omap4_vc_i2c_timing_init(voltdm); |
|
|
|
initialized = true; |
|
} |
|
|
|
/** |
|
* omap_vc_calc_vsel - calculate vsel value for a channel |
|
* @voltdm: channel to calculate value for |
|
* @uvolt: microvolt value to convert to vsel |
|
* |
|
* Converts a microvolt value to vsel value for the used PMIC. |
|
* This checks whether the microvolt value is out of bounds, and |
|
* adjusts the value accordingly. If unsupported value detected, |
|
* warning is thrown. |
|
*/ |
|
static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt) |
|
{ |
|
if (voltdm->pmic->vddmin > uvolt) |
|
uvolt = voltdm->pmic->vddmin; |
|
if (voltdm->pmic->vddmax < uvolt) { |
|
WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n", |
|
__func__, uvolt, voltdm->pmic->vddmax); |
|
/* Lets try maximum value anyway */ |
|
uvolt = voltdm->pmic->vddmax; |
|
} |
|
|
|
return voltdm->pmic->uv_to_vsel(uvolt); |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
/** |
|
* omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB |
|
* @mm: length of the PCB trace in millimetres |
|
* |
|
* Sets the PCB trace length for the I2C channel. By default uses 63mm. |
|
* This is needed for properly calculating the capacitance value for |
|
* the PCB trace, and for setting the SR I2C channel timing parameters. |
|
*/ |
|
void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm) |
|
{ |
|
sr_i2c_pcb_length = mm; |
|
} |
|
#endif |
|
|
|
void __init omap_vc_init_channel(struct voltagedomain *voltdm) |
|
{ |
|
struct omap_vc_channel *vc = voltdm->vc; |
|
u8 on_vsel, onlp_vsel, ret_vsel, off_vsel; |
|
u32 val; |
|
|
|
if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) { |
|
pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name); |
|
return; |
|
} |
|
|
|
if (!voltdm->read || !voltdm->write) { |
|
pr_err("%s: No read/write API for accessing vdd_%s regs\n", |
|
__func__, voltdm->name); |
|
return; |
|
} |
|
|
|
vc->cfg_channel = 0; |
|
if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT) |
|
vc_cfg_bits = &vc_mutant_channel_cfg; |
|
else |
|
vc_cfg_bits = &vc_default_channel_cfg; |
|
|
|
/* get PMIC/board specific settings */ |
|
vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr; |
|
vc->volt_reg_addr = voltdm->pmic->volt_reg_addr; |
|
vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr; |
|
|
|
/* Configure the i2c slave address for this VC */ |
|
voltdm->rmw(vc->smps_sa_mask, |
|
vc->i2c_slave_addr << __ffs(vc->smps_sa_mask), |
|
vc->smps_sa_reg); |
|
vc->cfg_channel |= vc_cfg_bits->sa; |
|
|
|
/* |
|
* Configure the PMIC register addresses. |
|
*/ |
|
voltdm->rmw(vc->smps_volra_mask, |
|
vc->volt_reg_addr << __ffs(vc->smps_volra_mask), |
|
vc->smps_volra_reg); |
|
vc->cfg_channel |= vc_cfg_bits->rav; |
|
|
|
if (vc->cmd_reg_addr) { |
|
voltdm->rmw(vc->smps_cmdra_mask, |
|
vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask), |
|
vc->smps_cmdra_reg); |
|
vc->cfg_channel |= vc_cfg_bits->rac; |
|
} |
|
|
|
if (vc->cmd_reg_addr == vc->volt_reg_addr) |
|
vc->cfg_channel |= vc_cfg_bits->racen; |
|
|
|
/* Set up the on, inactive, retention and off voltage */ |
|
on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on); |
|
onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp); |
|
ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret); |
|
off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off); |
|
|
|
val = ((on_vsel << vc->common->cmd_on_shift) | |
|
(onlp_vsel << vc->common->cmd_onlp_shift) | |
|
(ret_vsel << vc->common->cmd_ret_shift) | |
|
(off_vsel << vc->common->cmd_off_shift)); |
|
voltdm->write(val, vc->cmdval_reg); |
|
vc->cfg_channel |= vc_cfg_bits->cmd; |
|
|
|
/* Channel configuration */ |
|
omap_vc_config_channel(voltdm); |
|
|
|
omap_vc_i2c_init(voltdm); |
|
|
|
if (cpu_is_omap34xx()) |
|
omap3_vc_init_channel(voltdm); |
|
else if (cpu_is_omap44xx()) |
|
omap4_vc_init_channel(voltdm); |
|
} |
|
|
|
|