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166 lines
4.3 KiB
166 lines
4.3 KiB
/* |
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* linux/arch/arm/mach-omap2/timer.c |
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* |
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* OMAP2 GP timer support. |
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* |
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* Copyright (C) 2009 Nokia Corporation |
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* |
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* Update to use new clocksource/clockevent layers |
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* Author: Kevin Hilman, MontaVista Software, Inc. <[email protected]> |
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* Copyright (C) 2007 MontaVista Software, Inc. |
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* |
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* Original driver: |
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* Copyright (C) 2005 Nokia Corporation |
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* Author: Paul Mundt <[email protected]> |
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* Juha Yrjölä <[email protected]> |
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* OMAP Dual-mode timer framework support by Timo Teras |
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* |
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* Some parts based off of TI's 24xx code: |
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* |
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* Copyright (C) 2004-2009 Texas Instruments, Inc. |
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* |
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* Roughly modelled after the OMAP1 MPU timer code. |
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* Added OMAP4 support - Santosh Shilimkar <[email protected]> |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clocksource.h> |
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#include "soc.h" |
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#include "common.h" |
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#include "control.h" |
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#include "omap-secure.h" |
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#define REALTIME_COUNTER_BASE 0x48243200 |
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#define INCREMENTER_NUMERATOR_OFFSET 0x10 |
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#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 |
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#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 |
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static unsigned long arch_timer_freq; |
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void set_cntfreq(void) |
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{ |
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omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq); |
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} |
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/* |
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* The realtime counter also called master counter, is a free-running |
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* counter, which is related to real time. It produces the count used |
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* by the CPU local timer peripherals in the MPU cluster. The timer counts |
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* at a rate of 6.144 MHz. Because the device operates on different clocks |
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* in different power modes, the master counter shifts operation between |
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* clocks, adjusting the increment per clock in hardware accordingly to |
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* maintain a constant count rate. |
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*/ |
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static void __init realtime_counter_init(void) |
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{ |
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void __iomem *base; |
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static struct clk *sys_clk; |
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unsigned long rate; |
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unsigned int reg; |
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unsigned long long num, den; |
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base = ioremap(REALTIME_COUNTER_BASE, SZ_32); |
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if (!base) { |
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pr_err("%s: ioremap failed\n", __func__); |
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return; |
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} |
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sys_clk = clk_get(NULL, "sys_clkin"); |
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if (IS_ERR(sys_clk)) { |
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pr_err("%s: failed to get system clock handle\n", __func__); |
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iounmap(base); |
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return; |
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} |
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rate = clk_get_rate(sys_clk); |
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if (soc_is_dra7xx()) { |
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/* |
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* Errata i856 says the 32.768KHz crystal does not start at |
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* power on, so the CPU falls back to an emulated 32KHz clock |
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* based on sysclk / 610 instead. This causes the master counter |
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* frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 |
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* (OR sysclk * 75 / 244) |
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* |
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* This affects at least the DRA7/AM572x 1.0, 1.1 revisions. |
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* Of course any board built without a populated 32.768KHz |
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* crystal would also need this fix even if the CPU is fixed |
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* later. |
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* |
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* Either case can be detected by using the two speedselect bits |
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* If they are not 0, then the 32.768KHz clock driving the |
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* coarse counter that corrects the fine counter every time it |
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* ticks is actually rate/610 rather than 32.768KHz and we |
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* should compensate to avoid the 570ppm (at 20MHz, much worse |
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* at other rates) too fast system time. |
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*/ |
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reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); |
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if (reg & DRA7_SPEEDSELECT_MASK) { |
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num = 75; |
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den = 244; |
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goto sysclk1_based; |
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} |
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} |
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/* Numerator/denumerator values refer TRM Realtime Counter section */ |
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switch (rate) { |
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case 12000000: |
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num = 64; |
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den = 125; |
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break; |
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case 13000000: |
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num = 768; |
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den = 1625; |
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break; |
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case 19200000: |
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num = 8; |
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den = 25; |
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break; |
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case 20000000: |
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num = 192; |
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den = 625; |
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break; |
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case 26000000: |
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num = 384; |
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den = 1625; |
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break; |
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case 27000000: |
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num = 256; |
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den = 1125; |
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break; |
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case 38400000: |
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default: |
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/* Program it for 38.4 MHz */ |
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num = 4; |
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den = 25; |
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break; |
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} |
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sysclk1_based: |
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/* Program numerator and denumerator registers */ |
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reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) & |
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NUMERATOR_DENUMERATOR_MASK; |
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reg |= num; |
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writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET); |
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reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & |
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NUMERATOR_DENUMERATOR_MASK; |
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reg |= den; |
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writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); |
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arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); |
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set_cntfreq(); |
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iounmap(base); |
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} |
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void __init omap5_realtime_timer_init(void) |
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{ |
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omap_clk_init(); |
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realtime_counter_init(); |
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timer_probe(); |
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}
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