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493 lines
11 KiB
493 lines
11 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Low level suspend code for AM43XX SoCs |
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* |
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* Copyright (C) 2013-2018 Texas Instruments Incorporated - https://www.ti.com/ |
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* Dave Gerlach, Vaibhav Bedia |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/ti-emif-sram.h> |
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#include <linux/platform_data/pm33xx.h> |
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#include <asm/assembler.h> |
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#include <asm/hardware/cache-l2x0.h> |
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#include <asm/memory.h> |
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#include "cm33xx.h" |
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#include "common.h" |
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#include "iomap.h" |
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#include "omap-secure.h" |
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#include "omap44xx.h" |
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#include "pm-asm-offsets.h" |
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#include "prm33xx.h" |
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#include "prcm43xx.h" |
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/* replicated define because linux/bitops.h cannot be included in assembly */ |
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#define BIT(nr) (1 << (nr)) |
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#define AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED 0x00030000 |
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#define AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE 0x0003 |
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#define AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE 0x0002 |
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#define AM43XX_EMIF_POWEROFF_ENABLE 0x1 |
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#define AM43XX_EMIF_POWEROFF_DISABLE 0x0 |
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#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP 0x1 |
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#define AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO 0x3 |
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#define AM43XX_CM_BASE 0x44DF0000 |
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#define AM43XX_CM_REGADDR(inst, reg) \ |
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AM33XX_L4_WK_IO_ADDRESS(AM43XX_CM_BASE + (inst) + (reg)) |
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#define AM43XX_CM_MPU_CLKSTCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ |
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AM43XX_CM_MPU_MPU_CDOFFS) |
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#define AM43XX_CM_MPU_MPU_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_MPU_INST, \ |
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AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET) |
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#define AM43XX_CM_PER_EMIF_CLKCTRL AM43XX_CM_REGADDR(AM43XX_CM_PER_INST, \ |
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AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) |
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#define AM43XX_PRM_EMIF_CTRL_OFFSET 0x0030 |
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#define RTC_SECONDS_REG 0x0 |
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#define RTC_PMIC_REG 0x98 |
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#define RTC_PMIC_POWER_EN BIT(16) |
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#define RTC_PMIC_EXT_WAKEUP_STS BIT(12) |
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#define RTC_PMIC_EXT_WAKEUP_POL BIT(4) |
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#define RTC_PMIC_EXT_WAKEUP_EN BIT(0) |
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.arm |
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.arch armv7-a |
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.arch_extension sec |
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.align 3 |
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ENTRY(am43xx_do_wfi) |
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stmfd sp!, {r4 - r11, lr} @ save registers on stack |
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/* Save wfi_flags arg to data space */ |
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mov r4, r0 |
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adr r3, am43xx_pm_ro_sram_data |
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ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] |
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str r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] |
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#ifdef CONFIG_CACHE_L2X0 |
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/* Retrieve l2 cache virt address BEFORE we shut off EMIF */ |
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ldr r1, get_l2cache_base |
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blx r1 |
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mov r8, r0 |
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#endif |
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/* Only flush cache is we know we are losing MPU context */ |
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tst r4, #WFI_FLAG_FLUSH_CACHE |
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beq cache_skip_flush |
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/* |
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* Flush all data from the L1 and L2 data cache before disabling |
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* SCTLR.C bit. |
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*/ |
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ldr r1, kernel_flush |
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blx r1 |
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/* |
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* Clear the SCTLR.C bit to prevent further data cache |
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* allocation. Clearing SCTLR.C would make all the data accesses |
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* strongly ordered and would not hit the cache. |
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*/ |
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mrc p15, 0, r0, c1, c0, 0 |
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bic r0, r0, #(1 << 2) @ Disable the C bit |
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mcr p15, 0, r0, c1, c0, 0 |
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isb |
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dsb |
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/* |
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* Invalidate L1 and L2 data cache. |
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*/ |
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ldr r1, kernel_flush |
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blx r1 |
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#ifdef CONFIG_CACHE_L2X0 |
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/* |
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* Clean and invalidate the L2 cache. |
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*/ |
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#ifdef CONFIG_PL310_ERRATA_727915 |
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mov r0, #0x03 |
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX |
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dsb |
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smc #0 |
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dsb |
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#endif |
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mov r0, r8 |
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adr r4, am43xx_pm_ro_sram_data |
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ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] |
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mov r2, r0 |
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ldr r0, [r2, #L2X0_AUX_CTRL] |
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str r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET] |
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ldr r0, [r2, #L310_PREFETCH_CTRL] |
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str r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET] |
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ldr r0, l2_val |
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str r0, [r2, #L2X0_CLEAN_INV_WAY] |
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wait: |
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ldr r0, [r2, #L2X0_CLEAN_INV_WAY] |
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ldr r1, l2_val |
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ands r0, r0, r1 |
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bne wait |
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#ifdef CONFIG_PL310_ERRATA_727915 |
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mov r0, #0x00 |
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX |
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dsb |
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smc #0 |
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dsb |
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#endif |
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l2x_sync: |
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mov r0, r8 |
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mov r2, r0 |
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mov r0, #0x0 |
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str r0, [r2, #L2X0_CACHE_SYNC] |
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sync: |
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ldr r0, [r2, #L2X0_CACHE_SYNC] |
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ands r0, r0, #0x1 |
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bne sync |
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#endif |
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/* Restore wfi_flags */ |
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adr r3, am43xx_pm_ro_sram_data |
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ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET] |
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ldr r4, [r2, #AMX3_PM_WFI_FLAGS_OFFSET] |
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cache_skip_flush: |
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/* |
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* If we are trying to enter RTC+DDR mode we must perform |
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* a read from the rtc address space to ensure translation |
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* presence in the TLB to avoid page table walk after DDR |
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* is unavailable. |
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*/ |
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tst r4, #WFI_FLAG_RTC_ONLY |
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beq skip_rtc_va_refresh |
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adr r3, am43xx_pm_ro_sram_data |
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ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] |
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ldr r0, [r1] |
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skip_rtc_va_refresh: |
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/* Check if we want self refresh */ |
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tst r4, #WFI_FLAG_SELF_REFRESH |
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beq emif_skip_enter_sr |
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adr r9, am43xx_emif_sram_table |
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ldr r3, [r9, #EMIF_PM_ENTER_SR_OFFSET] |
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blx r3 |
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emif_skip_enter_sr: |
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/* Only necessary if PER is losing context */ |
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tst r4, #WFI_FLAG_SAVE_EMIF |
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beq emif_skip_save |
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ldr r3, [r9, #EMIF_PM_SAVE_CONTEXT_OFFSET] |
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blx r3 |
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emif_skip_save: |
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/* Only can disable EMIF if we have entered self refresh */ |
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tst r4, #WFI_FLAG_SELF_REFRESH |
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beq emif_skip_disable |
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/* Disable EMIF */ |
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ldr r1, am43xx_virt_emif_clkctrl |
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ldr r2, [r1] |
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bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE |
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str r2, [r1] |
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wait_emif_disable: |
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ldr r2, [r1] |
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mov r3, #AM33XX_CM_CLKCTRL_MODULESTATE_DISABLED |
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cmp r2, r3 |
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bne wait_emif_disable |
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emif_skip_disable: |
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tst r4, #WFI_FLAG_RTC_ONLY |
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beq skip_rtc_only |
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adr r3, am43xx_pm_ro_sram_data |
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ldr r1, [r3, #AMX3_PM_RTC_BASE_VIRT_OFFSET] |
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ldr r0, [r1, #RTC_PMIC_REG] |
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orr r0, r0, #RTC_PMIC_POWER_EN |
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orr r0, r0, #RTC_PMIC_EXT_WAKEUP_STS |
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orr r0, r0, #RTC_PMIC_EXT_WAKEUP_EN |
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orr r0, r0, #RTC_PMIC_EXT_WAKEUP_POL |
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str r0, [r1, #RTC_PMIC_REG] |
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ldr r0, [r1, #RTC_PMIC_REG] |
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/* Wait for 2 seconds to lose power */ |
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mov r3, #2 |
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ldr r2, [r1, #RTC_SECONDS_REG] |
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rtc_loop: |
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ldr r0, [r1, #RTC_SECONDS_REG] |
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cmp r0, r2 |
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beq rtc_loop |
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mov r2, r0 |
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subs r3, r3, #1 |
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bne rtc_loop |
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b re_enable_emif |
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skip_rtc_only: |
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tst r4, #WFI_FLAG_WAKE_M3 |
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beq wkup_m3_skip |
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/* |
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* For the MPU WFI to be registered as an interrupt |
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* to WKUP_M3, MPU_CLKCTRL.MODULEMODE needs to be set |
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* to DISABLED |
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*/ |
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ldr r1, am43xx_virt_mpu_clkctrl |
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ldr r2, [r1] |
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bic r2, r2, #AM33XX_CM_CLKCTRL_MODULEMODE_DISABLE |
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str r2, [r1] |
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/* |
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* Put MPU CLKDM to SW_SLEEP |
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*/ |
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ldr r1, am43xx_virt_mpu_clkstctrl |
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mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_SW_SLEEP |
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str r2, [r1] |
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wkup_m3_skip: |
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/* |
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* Execute a barrier instruction to ensure that all cache, |
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* TLB and branch predictor maintenance operations issued |
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* have completed. |
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*/ |
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dsb |
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dmb |
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/* |
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* Execute a WFI instruction and wait until the |
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* STANDBYWFI output is asserted to indicate that the |
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* CPU is in idle and low power state. CPU can specualatively |
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* prefetch the instructions so add NOPs after WFI. Sixteen |
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* NOPs as per Cortex-A9 pipeline. |
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*/ |
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wfi |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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nop |
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/* We come here in case of an abort due to a late interrupt */ |
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ldr r1, am43xx_virt_mpu_clkstctrl |
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mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO |
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str r2, [r1] |
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/* Set MPU_CLKCTRL.MODULEMODE back to ENABLE */ |
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ldr r1, am43xx_virt_mpu_clkctrl |
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mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE |
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str r2, [r1] |
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re_enable_emif: |
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/* Re-enable EMIF */ |
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ldr r1, am43xx_virt_emif_clkctrl |
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mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE |
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str r2, [r1] |
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wait_emif_enable: |
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ldr r3, [r1] |
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cmp r2, r3 |
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bne wait_emif_enable |
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tst r4, #WFI_FLAG_FLUSH_CACHE |
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beq cache_skip_restore |
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/* |
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* Set SCTLR.C bit to allow data cache allocation |
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*/ |
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mrc p15, 0, r0, c1, c0, 0 |
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orr r0, r0, #(1 << 2) @ Enable the C bit |
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mcr p15, 0, r0, c1, c0, 0 |
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isb |
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cache_skip_restore: |
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/* Only necessary if PER is losing context */ |
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tst r4, #WFI_FLAG_SELF_REFRESH |
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beq emif_skip_exit_sr_abt |
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adr r9, am43xx_emif_sram_table |
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ldr r1, [r9, #EMIF_PM_ABORT_SR_OFFSET] |
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blx r1 |
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emif_skip_exit_sr_abt: |
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/* Let the suspend code know about the abort */ |
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mov r0, #1 |
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ldmfd sp!, {r4 - r11, pc} @ restore regs and return |
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ENDPROC(am43xx_do_wfi) |
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.align |
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ENTRY(am43xx_resume_offset) |
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.word . - am43xx_do_wfi |
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ENTRY(am43xx_resume_from_deep_sleep) |
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/* Set MPU CLKSTCTRL to HW AUTO so that CPUidle works properly */ |
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ldr r1, am43xx_virt_mpu_clkstctrl |
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mov r2, #AM43XX_CM_CLKSTCTRL_CLKTRCTRL_HW_AUTO |
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str r2, [r1] |
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/* For AM43xx, use EMIF power down until context is restored */ |
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ldr r2, am43xx_phys_emif_poweroff |
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mov r1, #AM43XX_EMIF_POWEROFF_ENABLE |
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str r1, [r2, #0x0] |
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/* Re-enable EMIF */ |
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ldr r1, am43xx_phys_emif_clkctrl |
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mov r2, #AM33XX_CM_CLKCTRL_MODULEMODE_ENABLE |
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str r2, [r1] |
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wait_emif_enable1: |
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ldr r3, [r1] |
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cmp r2, r3 |
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bne wait_emif_enable1 |
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adr r9, am43xx_emif_sram_table |
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ldr r1, [r9, #EMIF_PM_RESTORE_CONTEXT_OFFSET] |
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blx r1 |
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ldr r1, [r9, #EMIF_PM_EXIT_SR_OFFSET] |
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blx r1 |
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ldr r2, am43xx_phys_emif_poweroff |
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mov r1, #AM43XX_EMIF_POWEROFF_DISABLE |
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str r1, [r2, #0x0] |
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ldr r1, [r9, #EMIF_PM_RUN_HW_LEVELING] |
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blx r1 |
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#ifdef CONFIG_CACHE_L2X0 |
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ldr r2, l2_cache_base |
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ldr r0, [r2, #L2X0_CTRL] |
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and r0, #0x0f |
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cmp r0, #1 |
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beq skip_l2en @ Skip if already enabled |
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adr r4, am43xx_pm_ro_sram_data |
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ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_PHYS_OFFSET] |
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ldr r0, [r3, #AMX3_PM_L2_PREFETCH_CTRL_VAL_OFFSET] |
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ldr r12, l2_smc1 |
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dsb |
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smc #0 |
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dsb |
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set_aux_ctrl: |
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ldr r0, [r3, #AMX3_PM_L2_AUX_CTRL_VAL_OFFSET] |
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ldr r12, l2_smc2 |
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dsb |
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smc #0 |
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dsb |
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/* L2 invalidate on resume */ |
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ldr r0, l2_val |
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ldr r2, l2_cache_base |
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str r0, [r2, #L2X0_INV_WAY] |
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wait2: |
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ldr r0, [r2, #L2X0_INV_WAY] |
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ldr r1, l2_val |
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ands r0, r0, r1 |
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bne wait2 |
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#ifdef CONFIG_PL310_ERRATA_727915 |
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mov r0, #0x00 |
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mov r12, #OMAP4_MON_L2X0_DBG_CTRL_INDEX |
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dsb |
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smc #0 |
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dsb |
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#endif |
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l2x_sync2: |
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ldr r2, l2_cache_base |
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mov r0, #0x0 |
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str r0, [r2, #L2X0_CACHE_SYNC] |
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sync2: |
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ldr r0, [r2, #L2X0_CACHE_SYNC] |
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ands r0, r0, #0x1 |
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bne sync2 |
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mov r0, #0x1 |
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ldr r12, l2_smc3 |
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dsb |
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smc #0 |
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dsb |
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#endif |
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skip_l2en: |
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/* We are back. Branch to the common CPU resume routine */ |
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mov r0, #0 |
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ldr pc, resume_addr |
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ENDPROC(am43xx_resume_from_deep_sleep) |
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/* |
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* Local variables |
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*/ |
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.align |
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kernel_flush: |
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.word v7_flush_dcache_all |
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ddr_start: |
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.word PAGE_OFFSET |
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am43xx_phys_emif_poweroff: |
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.word (AM43XX_CM_BASE + AM43XX_PRM_DEVICE_INST + \ |
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AM43XX_PRM_EMIF_CTRL_OFFSET) |
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am43xx_virt_mpu_clkstctrl: |
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.word (AM43XX_CM_MPU_CLKSTCTRL) |
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am43xx_virt_mpu_clkctrl: |
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.word (AM43XX_CM_MPU_MPU_CLKCTRL) |
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am43xx_virt_emif_clkctrl: |
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.word (AM43XX_CM_PER_EMIF_CLKCTRL) |
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am43xx_phys_emif_clkctrl: |
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.word (AM43XX_CM_BASE + AM43XX_CM_PER_INST + \ |
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AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET) |
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#ifdef CONFIG_CACHE_L2X0 |
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/* L2 cache related defines for AM437x */ |
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get_l2cache_base: |
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.word omap4_get_l2cache_base |
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l2_cache_base: |
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.word OMAP44XX_L2CACHE_BASE |
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l2_smc1: |
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.word OMAP4_MON_L2X0_PREFETCH_INDEX |
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l2_smc2: |
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.word OMAP4_MON_L2X0_AUXCTRL_INDEX |
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l2_smc3: |
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.word OMAP4_MON_L2X0_CTRL_INDEX |
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l2_val: |
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.word 0xffff |
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#endif |
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.align 3 |
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/* DDR related defines */ |
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ENTRY(am43xx_emif_sram_table) |
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.space EMIF_PM_FUNCTIONS_SIZE |
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ENTRY(am43xx_pm_sram) |
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.word am43xx_do_wfi |
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.word am43xx_do_wfi_sz |
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.word am43xx_resume_offset |
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.word am43xx_emif_sram_table |
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.word am43xx_pm_ro_sram_data |
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resume_addr: |
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.word cpu_resume - PAGE_OFFSET + 0x80000000 |
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.align 3 |
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ENTRY(am43xx_pm_ro_sram_data) |
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.space AMX3_PM_RO_SRAM_DATA_SIZE |
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ENTRY(am43xx_do_wfi_sz) |
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.word . - am43xx_do_wfi
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