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210 lines
6.6 KiB
210 lines
6.6 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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#ifndef __ARCH_ARM_MACH_OMAP2_SDRC_H |
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#define __ARCH_ARM_MACH_OMAP2_SDRC_H |
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/* |
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* OMAP2/3 SDRC/SMS macros and prototypes |
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* |
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* Copyright (C) 2007-2008, 2012 Texas Instruments, Inc. |
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* Copyright (C) 2007-2008 Nokia Corporation |
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* |
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* Paul Walmsley |
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* Tony Lindgren |
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* Richard Woodruff |
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*/ |
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#undef DEBUG |
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#ifndef __ASSEMBLER__ |
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#include <linux/io.h> |
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extern void __iomem *omap2_sdrc_base; |
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extern void __iomem *omap2_sms_base; |
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#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg)) |
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#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg)) |
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/* SDRC global register get/set */ |
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static inline void sdrc_write_reg(u32 val, u16 reg) |
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{ |
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writel_relaxed(val, OMAP_SDRC_REGADDR(reg)); |
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} |
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static inline u32 sdrc_read_reg(u16 reg) |
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{ |
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return readl_relaxed(OMAP_SDRC_REGADDR(reg)); |
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} |
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/* SMS global register get/set */ |
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static inline void sms_write_reg(u32 val, u16 reg) |
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{ |
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writel_relaxed(val, OMAP_SMS_REGADDR(reg)); |
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} |
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static inline u32 sms_read_reg(u16 reg) |
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{ |
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return readl_relaxed(OMAP_SMS_REGADDR(reg)); |
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} |
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extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms); |
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/** |
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* struct omap_sdrc_params - SDRC parameters for a given SDRC clock rate |
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* @rate: SDRC clock rate (in Hz) |
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* @actim_ctrla: Value to program to SDRC_ACTIM_CTRLA for this rate |
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* @actim_ctrlb: Value to program to SDRC_ACTIM_CTRLB for this rate |
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* @rfr_ctrl: Value to program to SDRC_RFR_CTRL for this rate |
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* @mr: Value to program to SDRC_MR for this rate |
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* |
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* This structure holds a pre-computed set of register values for the |
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* SDRC for a given SDRC clock rate and SDRAM chip. These are |
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* intended to be pre-computed and specified in an array in the board-*.c |
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* files. The structure is keyed off the 'rate' field. |
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*/ |
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struct omap_sdrc_params { |
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unsigned long rate; |
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u32 actim_ctrla; |
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u32 actim_ctrlb; |
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u32 rfr_ctrl; |
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u32 mr; |
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}; |
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#ifdef CONFIG_SOC_HAS_OMAP2_SDRC |
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void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
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struct omap_sdrc_params *sdrc_cs1); |
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#else |
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static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
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struct omap_sdrc_params *sdrc_cs1) {}; |
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#endif |
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int omap2_sdrc_get_params(unsigned long r, |
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struct omap_sdrc_params **sdrc_cs0, |
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struct omap_sdrc_params **sdrc_cs1); |
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void omap2_sms_save_context(void); |
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void omap2_sms_restore_context(void); |
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struct memory_timings { |
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u32 m_type; /* ddr = 1, sdr = 0 */ |
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u32 dll_mode; /* use lock mode = 1, unlock mode = 0 */ |
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u32 slow_dll_ctrl; /* unlock mode, dll value for slow speed */ |
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u32 fast_dll_ctrl; /* unlock mode, dll value for fast speed */ |
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u32 base_cs; /* base chip select to use for calculations */ |
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}; |
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extern void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode); |
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struct omap_sdrc_params *rx51_get_sdram_timings(void); |
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u32 omap2xxx_sdrc_dll_is_unlocked(void); |
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u32 omap2xxx_sdrc_reprogram(u32 level, u32 force); |
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#else |
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#define OMAP242X_SDRC_REGADDR(reg) \ |
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OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE + (reg)) |
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#define OMAP243X_SDRC_REGADDR(reg) \ |
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OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE + (reg)) |
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#define OMAP34XX_SDRC_REGADDR(reg) \ |
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OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE + (reg)) |
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#endif /* __ASSEMBLER__ */ |
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/* Minimum frequency that the SDRC DLL can lock at */ |
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000 |
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/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */ |
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#define SDRC_MPURATE_SCALE 8 |
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/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */ |
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#define SDRC_MPURATE_BASE_SHIFT 9 |
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/* |
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* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at |
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* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize |
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*/ |
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#define SDRC_MPURATE_LOOPS 96 |
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/* SDRC register offsets - read/write with sdrc_{read,write}_reg() */ |
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#define SDRC_SYSCONFIG 0x010 |
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#define SDRC_CS_CFG 0x040 |
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#define SDRC_SHARING 0x044 |
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#define SDRC_ERR_TYPE 0x04C |
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#define SDRC_DLLA_CTRL 0x060 |
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#define SDRC_DLLA_STATUS 0x064 |
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#define SDRC_DLLB_CTRL 0x068 |
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#define SDRC_DLLB_STATUS 0x06C |
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#define SDRC_POWER 0x070 |
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#define SDRC_MCFG_0 0x080 |
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#define SDRC_MR_0 0x084 |
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#define SDRC_EMR2_0 0x08c |
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#define SDRC_ACTIM_CTRL_A_0 0x09c |
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#define SDRC_ACTIM_CTRL_B_0 0x0a0 |
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#define SDRC_RFR_CTRL_0 0x0a4 |
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#define SDRC_MANUAL_0 0x0a8 |
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#define SDRC_MCFG_1 0x0B0 |
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#define SDRC_MR_1 0x0B4 |
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#define SDRC_EMR2_1 0x0BC |
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#define SDRC_ACTIM_CTRL_A_1 0x0C4 |
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#define SDRC_ACTIM_CTRL_B_1 0x0C8 |
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#define SDRC_RFR_CTRL_1 0x0D4 |
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#define SDRC_MANUAL_1 0x0D8 |
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#define SDRC_POWER_AUTOCOUNT_SHIFT 8 |
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#define SDRC_POWER_AUTOCOUNT_MASK (0xffff << SDRC_POWER_AUTOCOUNT_SHIFT) |
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#define SDRC_POWER_CLKCTRL_SHIFT 4 |
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#define SDRC_POWER_CLKCTRL_MASK (0x3 << SDRC_POWER_CLKCTRL_SHIFT) |
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#define SDRC_SELF_REFRESH_ON_AUTOCOUNT (0x2 << SDRC_POWER_CLKCTRL_SHIFT) |
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/* |
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* These values represent the number of memory clock cycles between |
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* autorefresh initiation. They assume 1 refresh per 64 ms (JEDEC), 8192 |
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* rows per device, and include a subtraction of a 50 cycle window in the |
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* event that the autorefresh command is delayed due to other SDRC activity. |
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* The '| 1' sets the ARE field to send one autorefresh when the autorefresh |
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* counter reaches 0. |
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* |
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* These represent optimal values for common parts, it won't work for all. |
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* As long as you scale down, most parameters are still work, they just |
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* become sub-optimal. The RFR value goes in the opposite direction. If you |
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* don't adjust it down as your clock period increases the refresh interval |
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* will not be met. Setting all parameters for complete worst case may work, |
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* but may cut memory performance by 2x. Due to errata the DLLs need to be |
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* unlocked and their value needs run time calibration. A dynamic call is |
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* need for that as no single right value exists across production samples. |
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* |
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* Only the FULL speed values are given. Current code is such that rate |
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* changes must be made at DPLLoutx2. The actual value adjustment for low |
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* frequency operation will be handled by omap_set_performance() |
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* |
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* By having the boot loader boot up in the fastest L4 speed available likely |
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* will result in something which you can switch between. |
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*/ |
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#define SDRC_RFR_CTRL_165MHz (0x00044c00 | 1) |
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#define SDRC_RFR_CTRL_133MHz (0x0003de00 | 1) |
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#define SDRC_RFR_CTRL_100MHz (0x0002da01 | 1) |
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#define SDRC_RFR_CTRL_110MHz (0x0002da01 | 1) /* Need to calc */ |
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#define SDRC_RFR_CTRL_BYPASS (0x00005000 | 1) /* Need to calc */ |
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/* |
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* SMS register access |
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*/ |
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#define OMAP242X_SMS_REGADDR(reg) \ |
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(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE + reg) |
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#define OMAP243X_SMS_REGADDR(reg) \ |
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(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE + reg) |
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#define OMAP343X_SMS_REGADDR(reg) \ |
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(void __iomem *)OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE + reg) |
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/* SMS register offsets - read/write with sms_{read,write}_reg() */ |
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#define SMS_SYSCONFIG 0x010 |
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/* REVISIT: fill in other SMS registers here */ |
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#endif
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