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154 lines
3.8 KiB
154 lines
3.8 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* SMS/SDRC (SDRAM controller) common code for OMAP2/3 |
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* |
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* Copyright (C) 2005, 2008 Texas Instruments Inc. |
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* Copyright (C) 2005, 2008 Nokia Corporation |
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* |
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* Tony Lindgren <[email protected]> |
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* Paul Walmsley |
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* Richard Woodruff <[email protected]> |
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*/ |
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#undef DEBUG |
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#include <linux/module.h> |
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#include <linux/kernel.h> |
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#include <linux/device.h> |
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#include <linux/list.h> |
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#include <linux/errno.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include "common.h" |
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#include "clock.h" |
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#include "sdrc.h" |
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static struct omap_sdrc_params *sdrc_init_params_cs0, *sdrc_init_params_cs1; |
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void __iomem *omap2_sdrc_base; |
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void __iomem *omap2_sms_base; |
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struct omap2_sms_regs { |
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u32 sms_sysconfig; |
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}; |
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static struct omap2_sms_regs sms_context; |
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/* SDRC_POWER register bits */ |
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#define SDRC_POWER_EXTCLKDIS_SHIFT 3 |
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#define SDRC_POWER_PWDENA_SHIFT 2 |
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#define SDRC_POWER_PAGEPOLICY_SHIFT 0 |
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/** |
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* omap2_sms_save_context - Save SMS registers |
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* |
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* Save SMS registers that need to be restored after off mode. |
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*/ |
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void omap2_sms_save_context(void) |
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{ |
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sms_context.sms_sysconfig = sms_read_reg(SMS_SYSCONFIG); |
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} |
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/** |
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* omap2_sms_restore_context - Restore SMS registers |
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* |
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* Restore SMS registers that need to be Restored after off mode. |
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*/ |
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void omap2_sms_restore_context(void) |
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{ |
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sms_write_reg(sms_context.sms_sysconfig, SMS_SYSCONFIG); |
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} |
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/** |
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* omap2_sdrc_get_params - return SDRC register values for a given clock rate |
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* @r: SDRC clock rate (in Hz) |
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* @sdrc_cs0: chip select 0 ram timings ** |
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* @sdrc_cs1: chip select 1 ram timings ** |
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* |
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* Return pre-calculated values for the SDRC_ACTIM_CTRLA, |
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* SDRC_ACTIM_CTRLB, SDRC_RFR_CTRL and SDRC_MR registers in sdrc_cs[01] |
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* structs,for a given SDRC clock rate 'r'. |
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* These parameters control various timing delays in the SDRAM controller |
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* that are expressed in terms of the number of SDRC clock cycles to |
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* wait; hence the clock rate dependency. |
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* |
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* Supports 2 different timing parameters for both chip selects. |
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* |
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* Note 1: the sdrc_init_params_cs[01] must be sorted rate descending. |
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* Note 2: If sdrc_init_params_cs_1 is not NULL it must be of same size |
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* as sdrc_init_params_cs_0. |
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* |
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* Fills in the struct omap_sdrc_params * for each chip select. |
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* Returns 0 upon success or -1 upon failure. |
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*/ |
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int omap2_sdrc_get_params(unsigned long r, |
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struct omap_sdrc_params **sdrc_cs0, |
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struct omap_sdrc_params **sdrc_cs1) |
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{ |
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struct omap_sdrc_params *sp0, *sp1; |
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if (!sdrc_init_params_cs0) |
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return -1; |
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sp0 = sdrc_init_params_cs0; |
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sp1 = sdrc_init_params_cs1; |
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while (sp0->rate && sp0->rate != r) { |
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sp0++; |
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if (sdrc_init_params_cs1) |
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sp1++; |
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} |
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if (!sp0->rate) |
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return -1; |
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*sdrc_cs0 = sp0; |
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*sdrc_cs1 = sp1; |
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return 0; |
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} |
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void __init omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms) |
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{ |
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omap2_sdrc_base = sdrc; |
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omap2_sms_base = sms; |
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} |
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/** |
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* omap2_sdrc_init - initialize SMS, SDRC devices on boot |
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* @sdrc_cs[01]: pointers to a null-terminated list of struct omap_sdrc_params |
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* Support for 2 chip selects timings |
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* |
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* Turn on smart idle modes for SDRAM scheduler and controller. |
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* Program a known-good configuration for the SDRC to deal with buggy |
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* bootloaders. |
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*/ |
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void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0, |
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struct omap_sdrc_params *sdrc_cs1) |
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{ |
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u32 l; |
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l = sms_read_reg(SMS_SYSCONFIG); |
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l &= ~(0x3 << 3); |
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l |= (0x2 << 3); |
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sms_write_reg(l, SMS_SYSCONFIG); |
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l = sdrc_read_reg(SDRC_SYSCONFIG); |
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l &= ~(0x3 << 3); |
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l |= (0x2 << 3); |
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sdrc_write_reg(l, SDRC_SYSCONFIG); |
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sdrc_init_params_cs0 = sdrc_cs0; |
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sdrc_init_params_cs1 = sdrc_cs1; |
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/* XXX Enable SRFRONIDLEREQ here also? */ |
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/* |
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* PWDENA should not be set due to 34xx erratum 1.150 - PWDENA |
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* can cause random memory corruption |
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*/ |
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l = (1 << SDRC_POWER_EXTCLKDIS_SHIFT) | |
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(1 << SDRC_POWER_PAGEPOLICY_SHIFT); |
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sdrc_write_reg(l, SDRC_POWER); |
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omap2_sms_save_context(); |
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}
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