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410 lines
11 KiB
410 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* DRA7xx Power domains framework |
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* |
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* Copyright (C) 2009-2013 Texas Instruments, Inc. |
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* Copyright (C) 2009-2011 Nokia Corporation |
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* |
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* Generated by code originally written by: |
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* Abhijit Pagare ([email protected]) |
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* Benoit Cousson ([email protected]) |
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* Paul Walmsley ([email protected]) |
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* |
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* This file is automatically generated from the OMAP hardware databases. |
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* We respectfully ask that any modifications to this file be coordinated |
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* with the public [email protected] mailing list and the |
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* authors above to ensure that the autogeneration scripts are kept |
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* up-to-date with the file contents. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include "powerdomain.h" |
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#include "prcm-common.h" |
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#include "prcm44xx.h" |
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#include "prm7xx.h" |
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#include "prcm_mpu7xx.h" |
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#include "soc.h" |
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/* iva_7xx_pwrdm: IVA-HD power domain */ |
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static struct powerdomain iva_7xx_pwrdm = { |
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.name = "iva_pwrdm", |
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.prcm_offs = DRA7XX_PRM_IVA_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 4, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* hwa_mem */ |
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[1] = PWRSTS_ON, /* sl2_mem */ |
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[2] = PWRSTS_ON, /* tcm1_mem */ |
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[3] = PWRSTS_ON, /* tcm2_mem */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* rtc_7xx_pwrdm: */ |
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static struct powerdomain rtc_7xx_pwrdm = { |
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.name = "rtc_pwrdm", |
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.prcm_offs = DRA7XX_PRM_RTC_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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}; |
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/* custefuse_7xx_pwrdm: Customer efuse controller power domain */ |
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static struct powerdomain custefuse_7xx_pwrdm = { |
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.name = "custefuse_pwrdm", |
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.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* custefuse_aon_7xx_pwrdm: Customer efuse controller power domain */ |
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static struct powerdomain custefuse_aon_7xx_pwrdm = { |
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.name = "custefuse_pwrdm", |
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.prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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}; |
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/* ipu_7xx_pwrdm: Audio back end power domain */ |
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static struct powerdomain ipu_7xx_pwrdm = { |
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.name = "ipu_pwrdm", |
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.prcm_offs = DRA7XX_PRM_IPU_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 2, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* aessmem */ |
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[1] = PWRSTS_ON, /* periphmem */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* dss_7xx_pwrdm: Display subsystem power domain */ |
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static struct powerdomain dss_7xx_pwrdm = { |
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.name = "dss_pwrdm", |
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.prcm_offs = DRA7XX_PRM_DSS_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* dss_mem */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* l4per_7xx_pwrdm: Target peripherals power domain */ |
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static struct powerdomain l4per_7xx_pwrdm = { |
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.name = "l4per_pwrdm", |
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.prcm_offs = DRA7XX_PRM_L4PER_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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.banks = 2, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* nonretained_bank */ |
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[1] = PWRSTS_ON, /* retained_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* gpu_7xx_pwrdm: 3D accelerator power domain */ |
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static struct powerdomain gpu_7xx_pwrdm = { |
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.name = "gpu_pwrdm", |
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.prcm_offs = DRA7XX_PRM_GPU_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* gpu_mem */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* wkupaon_7xx_pwrdm: Wake-up power domain */ |
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static struct powerdomain wkupaon_7xx_pwrdm = { |
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.name = "wkupaon_pwrdm", |
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.prcm_offs = DRA7XX_PRM_WKUPAON_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* wkup_bank */ |
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}, |
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}; |
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/* core_7xx_pwrdm: CORE power domain */ |
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static struct powerdomain core_7xx_pwrdm = { |
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.name = "core_pwrdm", |
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.prcm_offs = DRA7XX_PRM_CORE_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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.banks = 5, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* core_nret_bank */ |
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[1] = PWRSTS_ON, /* core_ocmram */ |
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[2] = PWRSTS_ON, /* core_other_bank */ |
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[3] = PWRSTS_ON, /* ipu_l2ram */ |
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[4] = PWRSTS_ON, /* ipu_unicache */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */ |
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static struct powerdomain coreaon_7xx_pwrdm = { |
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.name = "coreaon_pwrdm", |
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.prcm_offs = DRA7XX_PRM_COREAON_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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}; |
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/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */ |
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static struct powerdomain cpu0_7xx_pwrdm = { |
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.name = "cpu0_pwrdm", |
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.prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST, |
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.prcm_partition = DRA7XX_MPU_PRCM_PARTITION, |
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.pwrsts = PWRSTS_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, /* cpu0_l1 */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* cpu0_l1 */ |
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}, |
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}; |
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/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */ |
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static struct powerdomain cpu1_7xx_pwrdm = { |
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.name = "cpu1_pwrdm", |
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.prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST, |
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.prcm_partition = DRA7XX_MPU_PRCM_PARTITION, |
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.pwrsts = PWRSTS_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, /* cpu1_l1 */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* cpu1_l1 */ |
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}, |
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}; |
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/* vpe_7xx_pwrdm: */ |
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static struct powerdomain vpe_7xx_pwrdm = { |
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.name = "vpe_pwrdm", |
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.prcm_offs = DRA7XX_PRM_VPE_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* vpe_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */ |
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static struct powerdomain mpu_7xx_pwrdm = { |
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.name = "mpu_pwrdm", |
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.prcm_offs = DRA7XX_PRM_MPU_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 2, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, /* mpu_l2 */ |
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[1] = PWRSTS_RET, /* mpu_ram */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* mpu_l2 */ |
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[1] = PWRSTS_ON, /* mpu_ram */ |
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}, |
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}; |
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/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */ |
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static struct powerdomain l3init_7xx_pwrdm = { |
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.name = "l3init_pwrdm", |
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.prcm_offs = DRA7XX_PRM_L3INIT_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_ON, |
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.banks = 3, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* gmac_bank */ |
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[1] = PWRSTS_ON, /* l3init_bank1 */ |
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[2] = PWRSTS_ON, /* l3init_bank2 */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* eve3_7xx_pwrdm: */ |
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static struct powerdomain eve3_7xx_pwrdm = { |
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.name = "eve3_pwrdm", |
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.prcm_offs = DRA7XX_PRM_EVE3_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* eve3_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* emu_7xx_pwrdm: Emulation power domain */ |
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static struct powerdomain emu_7xx_pwrdm = { |
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.name = "emu_pwrdm", |
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.prcm_offs = DRA7XX_PRM_EMU_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* emu_bank */ |
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}, |
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}; |
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/* dsp2_7xx_pwrdm: */ |
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static struct powerdomain dsp2_7xx_pwrdm = { |
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.name = "dsp2_pwrdm", |
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.prcm_offs = DRA7XX_PRM_DSP2_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 3, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* dsp2_edma */ |
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[1] = PWRSTS_ON, /* dsp2_l1 */ |
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[2] = PWRSTS_ON, /* dsp2_l2 */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* dsp1_7xx_pwrdm: Tesla processor power domain */ |
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static struct powerdomain dsp1_7xx_pwrdm = { |
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.name = "dsp1_pwrdm", |
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.prcm_offs = DRA7XX_PRM_DSP1_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 3, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* dsp1_edma */ |
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[1] = PWRSTS_ON, /* dsp1_l1 */ |
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[2] = PWRSTS_ON, /* dsp1_l2 */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* cam_7xx_pwrdm: Camera subsystem power domain */ |
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static struct powerdomain cam_7xx_pwrdm = { |
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.name = "cam_pwrdm", |
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.prcm_offs = DRA7XX_PRM_CAM_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* vip_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* eve4_7xx_pwrdm: */ |
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static struct powerdomain eve4_7xx_pwrdm = { |
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.name = "eve4_pwrdm", |
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.prcm_offs = DRA7XX_PRM_EVE4_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* eve4_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* eve2_7xx_pwrdm: */ |
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static struct powerdomain eve2_7xx_pwrdm = { |
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.name = "eve2_pwrdm", |
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.prcm_offs = DRA7XX_PRM_EVE2_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* eve2_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* eve1_7xx_pwrdm: */ |
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static struct powerdomain eve1_7xx_pwrdm = { |
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.name = "eve1_pwrdm", |
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.prcm_offs = DRA7XX_PRM_EVE1_INST, |
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.prcm_partition = DRA7XX_PRM_PARTITION, |
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.pwrsts = PWRSTS_OFF_ON, |
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.banks = 1, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* eve1_bank */ |
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}, |
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.flags = PWRDM_HAS_LOWPOWERSTATECHANGE, |
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}; |
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/* |
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* The following power domains are not under SW control |
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* |
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* mpuaon |
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* mmaon |
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*/ |
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/* As powerdomains are added or removed above, this list must also be changed */ |
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static struct powerdomain *powerdomains_dra7xx[] __initdata = { |
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&iva_7xx_pwrdm, |
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&rtc_7xx_pwrdm, |
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&ipu_7xx_pwrdm, |
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&dss_7xx_pwrdm, |
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&l4per_7xx_pwrdm, |
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&gpu_7xx_pwrdm, |
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&wkupaon_7xx_pwrdm, |
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&core_7xx_pwrdm, |
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&coreaon_7xx_pwrdm, |
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&cpu0_7xx_pwrdm, |
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&cpu1_7xx_pwrdm, |
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&vpe_7xx_pwrdm, |
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&mpu_7xx_pwrdm, |
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&l3init_7xx_pwrdm, |
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&eve3_7xx_pwrdm, |
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&emu_7xx_pwrdm, |
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&dsp2_7xx_pwrdm, |
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&dsp1_7xx_pwrdm, |
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&cam_7xx_pwrdm, |
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&eve4_7xx_pwrdm, |
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&eve2_7xx_pwrdm, |
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&eve1_7xx_pwrdm, |
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NULL |
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}; |
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static struct powerdomain *powerdomains_dra76x[] __initdata = { |
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&custefuse_aon_7xx_pwrdm, |
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NULL |
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}; |
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static struct powerdomain *powerdomains_dra74x[] __initdata = { |
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&custefuse_7xx_pwrdm, |
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NULL |
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}; |
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static struct powerdomain *powerdomains_dra72x[] __initdata = { |
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&custefuse_aon_7xx_pwrdm, |
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NULL |
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}; |
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void __init dra7xx_powerdomains_init(void) |
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{ |
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pwrdm_register_platform_funcs(&omap4_pwrdm_operations); |
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pwrdm_register_pwrdms(powerdomains_dra7xx); |
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if (soc_is_dra76x()) |
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pwrdm_register_pwrdms(powerdomains_dra76x); |
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else if (soc_is_dra74x()) |
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pwrdm_register_pwrdms(powerdomains_dra74x); |
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else if (soc_is_dra72x()) |
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pwrdm_register_pwrdms(powerdomains_dra72x); |
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pwrdm_complete_init(); |
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}
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