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623 lines
15 KiB
623 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OMAP3 powerdomain definitions |
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* |
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* Copyright (C) 2007-2008, 2011 Texas Instruments, Inc. |
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* Copyright (C) 2007-2011 Nokia Corporation |
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* |
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* Paul Walmsley, Jouni Högander |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/bug.h> |
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#include "soc.h" |
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#include "powerdomain.h" |
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#include "powerdomains2xxx_3xxx_data.h" |
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#include "prcm-common.h" |
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#include "prm2xxx_3xxx.h" |
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#include "prm-regbits-34xx.h" |
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#include "cm2xxx_3xxx.h" |
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#include "cm-regbits-34xx.h" |
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|
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/* |
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* 34XX-specific powerdomains, dependencies |
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*/ |
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|
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/* |
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* Powerdomains |
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*/ |
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static struct powerdomain iva2_pwrdm = { |
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.name = "iva2_pwrdm", |
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.prcm_offs = OMAP3430_IVA2_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_OFF_RET, |
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.banks = 4, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, |
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[1] = PWRSTS_OFF_RET, |
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[2] = PWRSTS_OFF_RET, |
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[3] = PWRSTS_OFF_RET, |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, |
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[1] = PWRSTS_ON, |
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[2] = PWRSTS_OFF_ON, |
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[3] = PWRSTS_ON, |
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}, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain mpu_3xxx_pwrdm = { |
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.name = "mpu_pwrdm", |
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.prcm_offs = MPU_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_OFF_RET, |
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.flags = PWRDM_HAS_MPU_QUIRK, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_OFF_ON, |
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}, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain mpu_am35x_pwrdm = { |
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.name = "mpu_pwrdm", |
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.prcm_offs = MPU_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.flags = PWRDM_HAS_MPU_QUIRK, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_ON, |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, |
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}, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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/* |
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* The USBTLL Save-and-Restore mechanism is broken on |
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* 3430s up to ES3.0 and 3630ES1.0. Hence this feature |
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* needs to be disabled on these chips. |
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* Refer: 3430 errata ID i459 and 3630 errata ID i579 |
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* |
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* Note: setting the SAR flag could help for errata ID i478 |
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* which applies to 3430 <= ES3.1, but since the SAR feature |
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* is broken, do not use it. |
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*/ |
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static struct powerdomain core_3xxx_pre_es3_1_pwrdm = { |
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.name = "core_pwrdm", |
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.prcm_offs = CORE_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_OFF_RET, |
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.banks = 2, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ |
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain core_3xxx_es3_1_pwrdm = { |
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.name = "core_pwrdm", |
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.prcm_offs = CORE_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_OFF_RET, |
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/* |
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* Setting the SAR flag for errata ID i478 which applies |
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* to 3430 <= ES3.1 |
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*/ |
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.flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ |
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.banks = 2, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |
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[1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ |
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[1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain core_am35x_pwrdm = { |
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.name = "core_pwrdm", |
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.prcm_offs = CORE_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.banks = 2, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_ON, /* MEM1RETSTATE */ |
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[1] = PWRSTS_ON, /* MEM2RETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEM1ONSTATE */ |
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[1] = PWRSTS_ON, /* MEM2ONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain dss_pwrdm = { |
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.name = "dss_pwrdm", |
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.prcm_offs = OMAP3430_DSS_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_RET, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain dss_am35x_pwrdm = { |
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.name = "dss_pwrdm", |
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.prcm_offs = OMAP3430_DSS_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_ON, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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/* |
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* Although the 34XX TRM Rev K Table 4-371 notes that retention is a |
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* possible SGX powerstate, the SGX device itself does not support |
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* retention. |
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*/ |
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static struct powerdomain sgx_pwrdm = { |
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.name = "sgx_pwrdm", |
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.prcm_offs = OMAP3430ES2_SGX_MOD, |
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/* XXX This is accurate for 3430 SGX, but what about GFX? */ |
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.pwrsts = PWRSTS_OFF_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_RET, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain sgx_am35x_pwrdm = { |
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.name = "sgx_pwrdm", |
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.prcm_offs = OMAP3430ES2_SGX_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_ON, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain cam_pwrdm = { |
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.name = "cam_pwrdm", |
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.prcm_offs = OMAP3430_CAM_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_RET, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain per_pwrdm = { |
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.name = "per_pwrdm", |
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.prcm_offs = OMAP3430_PER_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_OFF_RET, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_RET, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain per_am35x_pwrdm = { |
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.name = "per_pwrdm", |
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.prcm_offs = OMAP3430_PER_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_ON, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain emu_pwrdm = { |
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.name = "emu_pwrdm", |
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.prcm_offs = OMAP3430_EMU_MOD, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain neon_pwrdm = { |
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.name = "neon_pwrdm", |
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.prcm_offs = OMAP3430_NEON_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain neon_am35x_pwrdm = { |
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.name = "neon_pwrdm", |
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.prcm_offs = OMAP3430_NEON_MOD, |
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.pwrsts = PWRSTS_ON, |
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.pwrsts_logic_ret = PWRSTS_ON, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain usbhost_pwrdm = { |
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.name = "usbhost_pwrdm", |
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.prcm_offs = OMAP3430ES2_USBHOST_MOD, |
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.pwrsts = PWRSTS_OFF_RET_ON, |
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.pwrsts_logic_ret = PWRSTS_RET, |
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/* |
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* REVISIT: Enabling usb host save and restore mechanism seems to |
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* leave the usb host domain permanently in ACTIVE mode after |
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* changing the usb host power domain state from OFF to active once. |
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* Disabling for now. |
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*/ |
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/*.flags = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */ |
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.banks = 1, |
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.pwrsts_mem_ret = { |
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[0] = PWRSTS_RET, /* MEMRETSTATE */ |
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}, |
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.pwrsts_mem_on = { |
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[0] = PWRSTS_ON, /* MEMONSTATE */ |
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}, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain dpll1_pwrdm = { |
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.name = "dpll1_pwrdm", |
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.prcm_offs = MPU_MOD, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain dpll2_pwrdm = { |
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.name = "dpll2_pwrdm", |
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.prcm_offs = OMAP3430_IVA2_MOD, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain dpll3_pwrdm = { |
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.name = "dpll3_pwrdm", |
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.prcm_offs = PLL_MOD, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain dpll4_pwrdm = { |
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.name = "dpll4_pwrdm", |
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.prcm_offs = PLL_MOD, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain dpll5_pwrdm = { |
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.name = "dpll5_pwrdm", |
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.prcm_offs = PLL_MOD, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain alwon_81xx_pwrdm = { |
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.name = "alwon_pwrdm", |
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.prcm_offs = TI81XX_PRM_ALWON_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain device_81xx_pwrdm = { |
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.name = "device_pwrdm", |
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.prcm_offs = TI81XX_PRM_DEVICE_MOD, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain gem_814x_pwrdm = { |
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.name = "gem_pwrdm", |
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.prcm_offs = TI814X_PRM_DSP_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "dsp" }, |
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}; |
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static struct powerdomain ivahd_814x_pwrdm = { |
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.name = "ivahd_pwrdm", |
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.prcm_offs = TI814X_PRM_HDVICP_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "iva" }, |
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}; |
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static struct powerdomain hdvpss_814x_pwrdm = { |
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.name = "hdvpss_pwrdm", |
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.prcm_offs = TI814X_PRM_HDVPSS_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "dsp" }, |
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}; |
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static struct powerdomain sgx_814x_pwrdm = { |
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.name = "sgx_pwrdm", |
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.prcm_offs = TI814X_PRM_GFX_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain isp_814x_pwrdm = { |
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.name = "isp_pwrdm", |
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.prcm_offs = TI814X_PRM_ISP_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain active_81xx_pwrdm = { |
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.name = "active_pwrdm", |
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.prcm_offs = TI816X_PRM_ACTIVE_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain default_81xx_pwrdm = { |
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.name = "default_pwrdm", |
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.prcm_offs = TI81XX_PRM_DEFAULT_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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static struct powerdomain ivahd0_816x_pwrdm = { |
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.name = "ivahd0_pwrdm", |
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.prcm_offs = TI816X_PRM_IVAHD0_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain ivahd1_816x_pwrdm = { |
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.name = "ivahd1_pwrdm", |
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.prcm_offs = TI816X_PRM_IVAHD1_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain ivahd2_816x_pwrdm = { |
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.name = "ivahd2_pwrdm", |
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.prcm_offs = TI816X_PRM_IVAHD2_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "mpu_iva" }, |
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}; |
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static struct powerdomain sgx_816x_pwrdm = { |
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.name = "sgx_pwrdm", |
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.prcm_offs = TI816X_PRM_SGX_MOD, |
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.pwrsts = PWRSTS_OFF_ON, |
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.voltdm = { .name = "core" }, |
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}; |
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|
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/* As powerdomains are added or removed above, this list must also be changed */ |
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static struct powerdomain *powerdomains_omap3430_common[] __initdata = { |
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&wkup_omap2_pwrdm, |
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&iva2_pwrdm, |
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&mpu_3xxx_pwrdm, |
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&neon_pwrdm, |
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&cam_pwrdm, |
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&dss_pwrdm, |
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&per_pwrdm, |
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&emu_pwrdm, |
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&dpll1_pwrdm, |
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&dpll2_pwrdm, |
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&dpll3_pwrdm, |
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&dpll4_pwrdm, |
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NULL |
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}; |
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|
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static struct powerdomain *powerdomains_omap3430es1[] __initdata = { |
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&gfx_omap2_pwrdm, |
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&core_3xxx_pre_es3_1_pwrdm, |
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NULL |
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}; |
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|
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/* also includes 3630ES1.0 */ |
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static struct powerdomain *powerdomains_omap3430es2_es3_0[] __initdata = { |
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&core_3xxx_pre_es3_1_pwrdm, |
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&sgx_pwrdm, |
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&usbhost_pwrdm, |
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&dpll5_pwrdm, |
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NULL |
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}; |
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|
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/* also includes 3630ES1.1+ */ |
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static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = { |
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&core_3xxx_es3_1_pwrdm, |
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&sgx_pwrdm, |
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&usbhost_pwrdm, |
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&dpll5_pwrdm, |
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NULL |
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}; |
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|
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static struct powerdomain *powerdomains_am35x[] __initdata = { |
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&wkup_omap2_pwrdm, |
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&mpu_am35x_pwrdm, |
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&neon_am35x_pwrdm, |
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&core_am35x_pwrdm, |
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&sgx_am35x_pwrdm, |
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&dss_am35x_pwrdm, |
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&per_am35x_pwrdm, |
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&emu_pwrdm, |
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&dpll1_pwrdm, |
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&dpll3_pwrdm, |
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&dpll4_pwrdm, |
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&dpll5_pwrdm, |
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NULL |
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}; |
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|
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static struct powerdomain *powerdomains_ti814x[] __initdata = { |
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&alwon_81xx_pwrdm, |
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&device_81xx_pwrdm, |
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&active_81xx_pwrdm, |
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&default_81xx_pwrdm, |
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&gem_814x_pwrdm, |
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&ivahd_814x_pwrdm, |
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&hdvpss_814x_pwrdm, |
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&sgx_814x_pwrdm, |
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&isp_814x_pwrdm, |
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NULL |
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}; |
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|
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static struct powerdomain *powerdomains_ti816x[] __initdata = { |
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&alwon_81xx_pwrdm, |
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&device_81xx_pwrdm, |
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&active_81xx_pwrdm, |
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&default_81xx_pwrdm, |
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&ivahd0_816x_pwrdm, |
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&ivahd1_816x_pwrdm, |
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&ivahd2_816x_pwrdm, |
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&sgx_816x_pwrdm, |
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NULL |
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}; |
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|
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/* TI81XX specific ops */ |
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#define TI81XX_PM_PWSTCTRL 0x0000 |
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#define TI81XX_RM_RSTCTRL 0x0010 |
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#define TI81XX_PM_PWSTST 0x0004 |
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|
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static int ti81xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) |
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{ |
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omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, |
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(pwrst << OMAP_POWERSTATE_SHIFT), |
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pwrdm->prcm_offs, TI81XX_PM_PWSTCTRL); |
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return 0; |
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} |
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|
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static int ti81xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) |
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{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
TI81XX_PM_PWSTCTRL, |
|
OMAP_POWERSTATE_MASK); |
|
} |
|
|
|
static int ti81xx_pwrdm_read_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : |
|
TI81XX_PM_PWSTST, |
|
OMAP_POWERSTATEST_MASK); |
|
} |
|
|
|
static int ti81xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) |
|
{ |
|
return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, |
|
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : |
|
TI81XX_PM_PWSTST, |
|
OMAP3430_LOGICSTATEST_MASK); |
|
} |
|
|
|
static int ti81xx_pwrdm_wait_transition(struct powerdomain *pwrdm) |
|
{ |
|
u32 c = 0; |
|
|
|
while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, |
|
(pwrdm->prcm_offs == TI814X_PRM_GFX_MOD) ? TI81XX_RM_RSTCTRL : |
|
TI81XX_PM_PWSTST) & |
|
OMAP_INTRANSITION_MASK) && |
|
(c++ < PWRDM_TRANSITION_BAILOUT)) |
|
udelay(1); |
|
|
|
if (c > PWRDM_TRANSITION_BAILOUT) { |
|
pr_err("powerdomain: %s timeout waiting for transition\n", |
|
pwrdm->name); |
|
return -EAGAIN; |
|
} |
|
|
|
pr_debug("powerdomain: completed transition in %d loops\n", c); |
|
|
|
return 0; |
|
} |
|
|
|
/* For dm814x we need to fix up fix GFX pwstst and rstctrl reg offsets */ |
|
static struct pwrdm_ops ti81xx_pwrdm_operations = { |
|
.pwrdm_set_next_pwrst = ti81xx_pwrdm_set_next_pwrst, |
|
.pwrdm_read_next_pwrst = ti81xx_pwrdm_read_next_pwrst, |
|
.pwrdm_read_pwrst = ti81xx_pwrdm_read_pwrst, |
|
.pwrdm_read_logic_pwrst = ti81xx_pwrdm_read_logic_pwrst, |
|
.pwrdm_wait_transition = ti81xx_pwrdm_wait_transition, |
|
}; |
|
|
|
void __init omap3xxx_powerdomains_init(void) |
|
{ |
|
unsigned int rev; |
|
|
|
if (!cpu_is_omap34xx() && !cpu_is_ti81xx()) |
|
return; |
|
|
|
/* Only 81xx needs custom pwrdm_operations */ |
|
if (!cpu_is_ti81xx()) |
|
pwrdm_register_platform_funcs(&omap3_pwrdm_operations); |
|
|
|
rev = omap_rev(); |
|
|
|
if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) { |
|
pwrdm_register_pwrdms(powerdomains_am35x); |
|
} else if (rev == TI8148_REV_ES1_0 || rev == TI8148_REV_ES2_0 || |
|
rev == TI8148_REV_ES2_1) { |
|
pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations); |
|
pwrdm_register_pwrdms(powerdomains_ti814x); |
|
} else if (rev == TI8168_REV_ES1_0 || rev == TI8168_REV_ES1_1 |
|
|| rev == TI8168_REV_ES2_0 || rev == TI8168_REV_ES2_1) { |
|
pwrdm_register_platform_funcs(&ti81xx_pwrdm_operations); |
|
pwrdm_register_pwrdms(powerdomains_ti816x); |
|
} else { |
|
pwrdm_register_pwrdms(powerdomains_omap3430_common); |
|
|
|
switch (rev) { |
|
case OMAP3430_REV_ES1_0: |
|
pwrdm_register_pwrdms(powerdomains_omap3430es1); |
|
break; |
|
case OMAP3430_REV_ES2_0: |
|
case OMAP3430_REV_ES2_1: |
|
case OMAP3430_REV_ES3_0: |
|
case OMAP3630_REV_ES1_0: |
|
pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0); |
|
break; |
|
case OMAP3430_REV_ES3_1: |
|
case OMAP3430_REV_ES3_1_2: |
|
case OMAP3630_REV_ES1_1: |
|
case OMAP3630_REV_ES1_2: |
|
pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus); |
|
break; |
|
default: |
|
WARN(1, "OMAP3 powerdomain init: unknown chip type\n"); |
|
} |
|
} |
|
|
|
pwrdm_complete_init(); |
|
}
|
|
|