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403 lines
8.8 KiB
403 lines
8.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* AM33XX Arch Power Management Routines |
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* |
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ |
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* Dave Gerlach |
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*/ |
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#include <linux/cpuidle.h> |
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#include <linux/platform_data/pm33xx.h> |
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#include <asm/cpuidle.h> |
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#include <asm/smp_scu.h> |
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#include <asm/suspend.h> |
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#include <linux/errno.h> |
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#include <linux/clk.h> |
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#include <linux/cpu.h> |
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#include <linux/platform_data/gpio-omap.h> |
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#include <linux/pinctrl/pinmux.h> |
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#include <linux/wkup_m3_ipc.h> |
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#include <linux/of.h> |
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#include <linux/rtc.h> |
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#include "cm33xx.h" |
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#include "common.h" |
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#include "control.h" |
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#include "clockdomain.h" |
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#include "iomap.h" |
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#include "pm.h" |
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#include "powerdomain.h" |
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#include "prm33xx.h" |
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#include "soc.h" |
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#include "sram.h" |
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#include "omap-secure.h" |
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static struct powerdomain *cefuse_pwrdm, *gfx_pwrdm, *per_pwrdm, *mpu_pwrdm; |
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static struct clockdomain *gfx_l4ls_clkdm; |
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static void __iomem *scu_base; |
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static int (*idle_fn)(u32 wfi_flags); |
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struct amx3_idle_state { |
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int wfi_flags; |
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}; |
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static struct amx3_idle_state *idle_states; |
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static int am43xx_map_scu(void) |
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{ |
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scu_base = ioremap(scu_a9_get_base(), SZ_256); |
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if (!scu_base) |
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return -ENOMEM; |
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return 0; |
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} |
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static int am33xx_check_off_mode_enable(void) |
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{ |
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if (enable_off_mode) |
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pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n"); |
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/* off mode not supported on am335x so return 0 always */ |
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return 0; |
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} |
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static int am43xx_check_off_mode_enable(void) |
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{ |
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/* |
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* Check for am437x-gp-evm which has the right Hardware design to |
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* support this mode reliably. |
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*/ |
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if (of_machine_is_compatible("ti,am437x-gp-evm") && enable_off_mode) |
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return enable_off_mode; |
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else if (enable_off_mode) |
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pr_warn("WARNING: This platform does not support off-mode, entering DeepSleep suspend.\n"); |
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return 0; |
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} |
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static int amx3_common_init(int (*idle)(u32 wfi_flags)) |
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{ |
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gfx_pwrdm = pwrdm_lookup("gfx_pwrdm"); |
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per_pwrdm = pwrdm_lookup("per_pwrdm"); |
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mpu_pwrdm = pwrdm_lookup("mpu_pwrdm"); |
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if ((!gfx_pwrdm) || (!per_pwrdm) || (!mpu_pwrdm)) |
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return -ENODEV; |
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(void)clkdm_for_each(omap_pm_clkdms_setup, NULL); |
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/* CEFUSE domain can be turned off post bootup */ |
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cefuse_pwrdm = pwrdm_lookup("cefuse_pwrdm"); |
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if (!cefuse_pwrdm) |
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pr_err("PM: Failed to get cefuse_pwrdm\n"); |
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else if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
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pr_info("PM: Leaving EFUSE power domain active\n"); |
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else |
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omap_set_pwrdm_state(cefuse_pwrdm, PWRDM_POWER_OFF); |
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idle_fn = idle; |
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return 0; |
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} |
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static int am33xx_suspend_init(int (*idle)(u32 wfi_flags)) |
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{ |
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int ret; |
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gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm"); |
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if (!gfx_l4ls_clkdm) { |
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pr_err("PM: Cannot lookup gfx_l4ls_clkdm clockdomains\n"); |
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return -ENODEV; |
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} |
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ret = amx3_common_init(idle); |
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return ret; |
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} |
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static int am43xx_suspend_init(int (*idle)(u32 wfi_flags)) |
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{ |
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int ret = 0; |
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ret = am43xx_map_scu(); |
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if (ret) { |
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pr_err("PM: Could not ioremap SCU\n"); |
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return ret; |
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} |
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ret = amx3_common_init(idle); |
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return ret; |
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} |
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static int amx3_suspend_deinit(void) |
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{ |
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idle_fn = NULL; |
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return 0; |
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} |
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static void amx3_pre_suspend_common(void) |
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{ |
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omap_set_pwrdm_state(gfx_pwrdm, PWRDM_POWER_OFF); |
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} |
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static void amx3_post_suspend_common(void) |
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{ |
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int status; |
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/* |
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* Because gfx_pwrdm is the only one under MPU control, |
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* comment on transition status |
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*/ |
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status = pwrdm_read_pwrst(gfx_pwrdm); |
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if (status != PWRDM_POWER_OFF) |
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pr_err("PM: GFX domain did not transition: %x\n", status); |
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} |
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static int am33xx_suspend(unsigned int state, int (*fn)(unsigned long), |
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unsigned long args) |
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{ |
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int ret = 0; |
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amx3_pre_suspend_common(); |
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ret = cpu_suspend(args, fn); |
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amx3_post_suspend_common(); |
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/* |
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* BUG: GFX_L4LS clock domain needs to be woken up to |
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* ensure thet L4LS clock domain does not get stuck in |
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* transition. If that happens L3 module does not get |
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* disabled, thereby leading to PER power domain |
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* transition failing |
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*/ |
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clkdm_wakeup(gfx_l4ls_clkdm); |
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clkdm_sleep(gfx_l4ls_clkdm); |
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return ret; |
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} |
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static int am43xx_suspend(unsigned int state, int (*fn)(unsigned long), |
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unsigned long args) |
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{ |
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int ret = 0; |
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/* Suspend secure side on HS devices */ |
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) { |
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if (optee_available) |
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omap_smccc_smc(AM43xx_PPA_SVC_PM_SUSPEND, 0); |
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else |
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omap_secure_dispatcher(AM43xx_PPA_SVC_PM_SUSPEND, |
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FLAG_START_CRITICAL, |
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0, 0, 0, 0, 0); |
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} |
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amx3_pre_suspend_common(); |
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scu_power_mode(scu_base, SCU_PM_POWEROFF); |
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ret = cpu_suspend(args, fn); |
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scu_power_mode(scu_base, SCU_PM_NORMAL); |
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if (!am43xx_check_off_mode_enable()) |
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amx3_post_suspend_common(); |
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/* |
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* Resume secure side on HS devices. |
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* |
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* Note that even on systems with OP-TEE available this resume call is |
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* issued to the ROM. This is because upon waking from suspend the ROM |
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* is restored as the secure monitor. On systems with OP-TEE ROM will |
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* restore OP-TEE during this call. |
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*/ |
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if (omap_type() != OMAP2_DEVICE_TYPE_GP) |
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omap_secure_dispatcher(AM43xx_PPA_SVC_PM_RESUME, |
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FLAG_START_CRITICAL, |
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0, 0, 0, 0, 0); |
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return ret; |
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} |
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static int am33xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args) |
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{ |
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int ret = 0; |
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if (omap_irq_pending() || need_resched()) |
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return ret; |
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ret = cpu_suspend(args, fn); |
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return ret; |
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} |
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static int am43xx_cpu_suspend(int (*fn)(unsigned long), unsigned long args) |
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{ |
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int ret = 0; |
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if (!scu_base) |
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return 0; |
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scu_power_mode(scu_base, SCU_PM_DORMANT); |
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ret = cpu_suspend(args, fn); |
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scu_power_mode(scu_base, SCU_PM_NORMAL); |
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return ret; |
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} |
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static void amx3_begin_suspend(void) |
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{ |
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cpu_idle_poll_ctrl(true); |
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} |
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static void amx3_finish_suspend(void) |
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{ |
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cpu_idle_poll_ctrl(false); |
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} |
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static struct am33xx_pm_sram_addr *amx3_get_sram_addrs(void) |
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{ |
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if (soc_is_am33xx()) |
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return &am33xx_pm_sram; |
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else if (soc_is_am437x()) |
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return &am43xx_pm_sram; |
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else |
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return NULL; |
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} |
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static void am43xx_save_context(void) |
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{ |
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} |
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static void am33xx_save_context(void) |
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{ |
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omap_intc_save_context(); |
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} |
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static void am33xx_restore_context(void) |
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{ |
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omap_intc_restore_context(); |
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} |
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static void am43xx_restore_context(void) |
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{ |
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/* |
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* HACK: restore dpll_per_clkdcoldo register contents, to avoid |
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* breaking suspend-resume |
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*/ |
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writel_relaxed(0x0, AM33XX_L4_WK_IO_ADDRESS(0x44df2e14)); |
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} |
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static struct am33xx_pm_platform_data am33xx_ops = { |
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.init = am33xx_suspend_init, |
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.deinit = amx3_suspend_deinit, |
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.soc_suspend = am33xx_suspend, |
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.cpu_suspend = am33xx_cpu_suspend, |
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.begin_suspend = amx3_begin_suspend, |
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.finish_suspend = amx3_finish_suspend, |
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.get_sram_addrs = amx3_get_sram_addrs, |
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.save_context = am33xx_save_context, |
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.restore_context = am33xx_restore_context, |
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.check_off_mode_enable = am33xx_check_off_mode_enable, |
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}; |
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static struct am33xx_pm_platform_data am43xx_ops = { |
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.init = am43xx_suspend_init, |
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.deinit = amx3_suspend_deinit, |
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.soc_suspend = am43xx_suspend, |
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.cpu_suspend = am43xx_cpu_suspend, |
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.begin_suspend = amx3_begin_suspend, |
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.finish_suspend = amx3_finish_suspend, |
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.get_sram_addrs = amx3_get_sram_addrs, |
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.save_context = am43xx_save_context, |
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.restore_context = am43xx_restore_context, |
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.check_off_mode_enable = am43xx_check_off_mode_enable, |
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}; |
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static struct am33xx_pm_platform_data *am33xx_pm_get_pdata(void) |
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{ |
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if (soc_is_am33xx()) |
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return &am33xx_ops; |
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else if (soc_is_am437x()) |
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return &am43xx_ops; |
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else |
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return NULL; |
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} |
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int __init amx3_common_pm_init(void) |
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{ |
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struct am33xx_pm_platform_data *pdata; |
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struct platform_device_info devinfo; |
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pdata = am33xx_pm_get_pdata(); |
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memset(&devinfo, 0, sizeof(devinfo)); |
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devinfo.name = "pm33xx"; |
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devinfo.data = pdata; |
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devinfo.size_data = sizeof(*pdata); |
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devinfo.id = -1; |
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platform_device_register_full(&devinfo); |
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return 0; |
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} |
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static int __init amx3_idle_init(struct device_node *cpu_node, int cpu) |
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{ |
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struct device_node *state_node; |
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struct amx3_idle_state states[CPUIDLE_STATE_MAX]; |
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int i; |
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int state_count = 1; |
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for (i = 0; ; i++) { |
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state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i); |
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if (!state_node) |
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break; |
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if (!of_device_is_available(state_node)) |
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continue; |
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if (i == CPUIDLE_STATE_MAX) { |
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pr_warn("%s: cpuidle states reached max possible\n", |
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__func__); |
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break; |
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} |
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states[state_count].wfi_flags = 0; |
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if (of_property_read_bool(state_node, "ti,idle-wkup-m3")) |
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states[state_count].wfi_flags |= WFI_FLAG_WAKE_M3 | |
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WFI_FLAG_FLUSH_CACHE; |
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state_count++; |
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} |
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idle_states = kcalloc(state_count, sizeof(*idle_states), GFP_KERNEL); |
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if (!idle_states) |
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return -ENOMEM; |
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for (i = 1; i < state_count; i++) |
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idle_states[i].wfi_flags = states[i].wfi_flags; |
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return 0; |
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} |
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static int amx3_idle_enter(unsigned long index) |
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{ |
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struct amx3_idle_state *idle_state = &idle_states[index]; |
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if (!idle_state) |
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return -EINVAL; |
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if (idle_fn) |
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idle_fn(idle_state->wfi_flags); |
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return 0; |
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} |
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static struct cpuidle_ops amx3_cpuidle_ops __initdata = { |
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.init = amx3_idle_init, |
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.suspend = amx3_idle_enter, |
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}; |
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CPUIDLE_METHOD_OF_DECLARE(pm33xx_idle, "ti,am3352", &amx3_cpuidle_ops); |
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CPUIDLE_METHOD_OF_DECLARE(pm43xx_idle, "ti,am4372", &amx3_cpuidle_ops);
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