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140 lines
3.3 KiB
140 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* This file configures the internal USB PHY in OMAP4430. Used |
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* with TWL6030 transceiver and MUSB on OMAP4430. |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com |
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* Author: Hema HK <[email protected]> |
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*/ |
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
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#include <linux/types.h> |
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#include <linux/delay.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <linux/usb.h> |
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#include <linux/usb/musb.h> |
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#include "soc.h" |
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#include "control.h" |
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#include "usb.h" |
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#define CONTROL_DEV_CONF 0x300 |
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#define PHY_PD 0x1 |
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/** |
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* omap4430_phy_power_down: disable MUSB PHY during early init |
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* |
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* OMAP4 MUSB PHY module is enabled by default on reset, but this will |
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* prevent core retention if not disabled by SW. USB driver will |
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* later on enable this, once and if the driver needs it. |
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*/ |
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static int __init omap4430_phy_power_down(void) |
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{ |
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void __iomem *ctrl_base; |
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if (!cpu_is_omap44xx()) |
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return 0; |
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ctrl_base = ioremap(OMAP443X_SCM_BASE, SZ_1K); |
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if (!ctrl_base) { |
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pr_err("control module ioremap failed\n"); |
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return -ENOMEM; |
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} |
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/* Power down the phy */ |
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writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF); |
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iounmap(ctrl_base); |
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return 0; |
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} |
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omap_early_initcall(omap4430_phy_power_down); |
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void am35x_musb_reset(void) |
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{ |
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u32 regval; |
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/* Reset the musb interface */ |
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); |
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regval |= AM35XX_USBOTGSS_SW_RST; |
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); |
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regval &= ~AM35XX_USBOTGSS_SW_RST; |
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omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET); |
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regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); |
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} |
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void am35x_musb_phy_power(u8 on) |
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{ |
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unsigned long timeout = jiffies + msecs_to_jiffies(100); |
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u32 devconf2; |
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if (on) { |
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/* |
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* Start the on-chip PHY and its PLL. |
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*/ |
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); |
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devconf2 &= ~(CONF2_RESET | CONF2_PHYPWRDN | CONF2_OTGPWRDN); |
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devconf2 |= CONF2_PHY_PLLON; |
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); |
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pr_info("Waiting for PHY clock good...\n"); |
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while (!(omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2) |
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& CONF2_PHYCLKGD)) { |
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cpu_relax(); |
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if (time_after(jiffies, timeout)) { |
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pr_err("musb PHY clock good timed out\n"); |
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break; |
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} |
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} |
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} else { |
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/* |
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* Power down the on-chip PHY. |
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*/ |
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devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); |
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devconf2 &= ~CONF2_PHY_PLLON; |
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devconf2 |= CONF2_PHYPWRDN | CONF2_OTGPWRDN; |
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); |
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} |
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} |
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void am35x_musb_clear_irq(void) |
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{ |
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u32 regval; |
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); |
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regval |= AM35XX_USBOTGSS_INT_CLR; |
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omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR); |
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regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); |
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} |
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void am35x_set_mode(u8 musb_mode) |
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{ |
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u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2); |
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devconf2 &= ~CONF2_OTGMODE; |
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switch (musb_mode) { |
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case MUSB_HOST: /* Force VBUS valid, ID = 0 */ |
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devconf2 |= CONF2_FORCE_HOST; |
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break; |
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case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */ |
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devconf2 |= CONF2_FORCE_DEVICE; |
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break; |
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case MUSB_OTG: /* Don't override the VBUS/ID comparators */ |
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devconf2 |= CONF2_NO_OVERRIDE; |
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break; |
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default: |
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pr_info("Unsupported mode %u\n", musb_mode); |
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} |
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omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2); |
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}
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