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674 lines
15 KiB
674 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx |
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* |
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* Copyright (C) 2011 Nokia Corporation |
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* Paul Walmsley |
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*/ |
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|
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#include <linux/types.h> |
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#include "omap_hwmod.h" |
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#include "omap_hwmod_common_data.h" |
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#include "cm-regbits-24xx.h" |
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#include "prm-regbits-24xx.h" |
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#include "wd_timer.h" |
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/* |
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* 'dispc' class |
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* display controller |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE | |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2_dispc_hwmod_class = { |
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.name = "dispc", |
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.sysc = &omap2_dispc_sysc, |
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}; |
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/* OMAP2xxx Timer Common */ |
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static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY | |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2xxx_timer_hwmod_class = { |
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.name = "timer", |
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.sysc = &omap2xxx_timer_sysc, |
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}; |
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/* |
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* 'wd_timer' class |
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* 32-bit watchdog upward counter that generates a pulse on the reset pin on |
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* overflow condition |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET | |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = { |
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.name = "wd_timer", |
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.sysc = &omap2xxx_wd_timer_sysc, |
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.pre_shutdown = &omap2_wd_timer_disable, |
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.reset = &omap2_wd_timer_reset, |
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}; |
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/* |
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* 'gpio' class |
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* general purpose io module |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
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SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2xxx_gpio_hwmod_class = { |
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.name = "gpio", |
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.sysc = &omap2xxx_gpio_sysc, |
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}; |
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/* |
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* 'mailbox' class |
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* mailbox module allowing communication between the on-chip processors |
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* using a queued mailbox-interrupt mechanism. |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = { |
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.rev_offs = 0x000, |
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.sysc_offs = 0x010, |
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.syss_offs = 0x014, |
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = { |
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.name = "mailbox", |
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.sysc = &omap2xxx_mailbox_sysc, |
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}; |
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/* |
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* 'mcspi' class |
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* multichannel serial port interface (mcspi) / master/slave synchronous serial |
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* bus |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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struct omap_hwmod_class omap2xxx_mcspi_class = { |
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.name = "mcspi", |
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.sysc = &omap2xxx_mcspi_sysc, |
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}; |
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/* |
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* 'gpmc' class |
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* general purpose memory controller |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = { |
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.rev_offs = 0x0000, |
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.sysc_offs = 0x0010, |
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.syss_offs = 0x0014, |
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = { |
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.name = "gpmc", |
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.sysc = &omap2xxx_gpmc_sysc, |
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}; |
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/* |
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* IP blocks |
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*/ |
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/* L3 */ |
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struct omap_hwmod omap2xxx_l3_main_hwmod = { |
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.name = "l3_main", |
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.class = &l3_hwmod_class, |
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.flags = HWMOD_NO_IDLEST, |
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}; |
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/* L4 CORE */ |
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struct omap_hwmod omap2xxx_l4_core_hwmod = { |
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.name = "l4_core", |
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.class = &l4_hwmod_class, |
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.flags = HWMOD_NO_IDLEST, |
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}; |
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/* L4 WKUP */ |
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struct omap_hwmod omap2xxx_l4_wkup_hwmod = { |
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.name = "l4_wkup", |
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.class = &l4_hwmod_class, |
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.flags = HWMOD_NO_IDLEST, |
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}; |
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/* MPU */ |
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struct omap_hwmod omap2xxx_mpu_hwmod = { |
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.name = "mpu", |
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.class = &mpu_hwmod_class, |
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.main_clk = "mpu_ck", |
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}; |
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/* IVA2 */ |
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struct omap_hwmod omap2xxx_iva_hwmod = { |
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.name = "iva", |
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.class = &iva_hwmod_class, |
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}; |
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/* timer3 */ |
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struct omap_hwmod omap2xxx_timer3_hwmod = { |
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.name = "timer3", |
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.main_clk = "gpt3_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer4 */ |
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struct omap_hwmod omap2xxx_timer4_hwmod = { |
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.name = "timer4", |
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.main_clk = "gpt4_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer5 */ |
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struct omap_hwmod omap2xxx_timer5_hwmod = { |
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.name = "timer5", |
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.main_clk = "gpt5_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer6 */ |
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struct omap_hwmod omap2xxx_timer6_hwmod = { |
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.name = "timer6", |
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.main_clk = "gpt6_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer7 */ |
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struct omap_hwmod omap2xxx_timer7_hwmod = { |
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.name = "timer7", |
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.main_clk = "gpt7_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer8 */ |
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struct omap_hwmod omap2xxx_timer8_hwmod = { |
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.name = "timer8", |
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.main_clk = "gpt8_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer9 */ |
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struct omap_hwmod omap2xxx_timer9_hwmod = { |
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.name = "timer9", |
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.main_clk = "gpt9_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer10 */ |
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struct omap_hwmod omap2xxx_timer10_hwmod = { |
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.name = "timer10", |
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.main_clk = "gpt10_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer11 */ |
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struct omap_hwmod omap2xxx_timer11_hwmod = { |
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.name = "timer11", |
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.main_clk = "gpt11_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* timer12 */ |
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struct omap_hwmod omap2xxx_timer12_hwmod = { |
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.name = "timer12", |
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.main_clk = "gpt12_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_timer_hwmod_class, |
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.flags = HWMOD_SET_DEFAULT_CLOCKACT, |
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}; |
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/* wd_timer2 */ |
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struct omap_hwmod omap2xxx_wd_timer2_hwmod = { |
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.name = "wd_timer2", |
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.class = &omap2xxx_wd_timer_hwmod_class, |
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.main_clk = "mpu_wdt_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = WKUP_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT, |
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}, |
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}, |
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}; |
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/* UART1 */ |
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struct omap_hwmod omap2xxx_uart1_hwmod = { |
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.name = "uart1", |
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.main_clk = "uart1_fck", |
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.flags = DEBUG_OMAP2UART1_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT, |
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}, |
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}, |
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.class = &omap2_uart_class, |
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}; |
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/* UART2 */ |
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struct omap_hwmod omap2xxx_uart2_hwmod = { |
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.name = "uart2", |
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.main_clk = "uart2_fck", |
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.flags = DEBUG_OMAP2UART2_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT, |
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}, |
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}, |
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.class = &omap2_uart_class, |
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}; |
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/* UART3 */ |
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struct omap_hwmod omap2xxx_uart3_hwmod = { |
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.name = "uart3", |
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.main_clk = "uart3_fck", |
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.flags = DEBUG_OMAP2UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT, |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT, |
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}, |
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}, |
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.class = &omap2_uart_class, |
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}; |
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/* dss */ |
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static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
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/* |
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* The DSS HW needs all DSS clocks enabled during reset. The dss_core |
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* driver does not use these clocks. |
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*/ |
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{ .role = "tv_clk", .clk = "dss_54m_fck" }, |
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{ .role = "sys_clk", .clk = "dss2_fck" }, |
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}; |
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struct omap_hwmod omap2xxx_dss_core_hwmod = { |
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.name = "dss_core", |
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.class = &omap2_dss_hwmod_class, |
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.main_clk = "dss1_fck", /* instead of dss_fck */ |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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}, |
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}, |
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.opt_clks = dss_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
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.flags = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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}; |
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struct omap_hwmod omap2xxx_dss_dispc_hwmod = { |
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.name = "dss_dispc", |
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.class = &omap2_dispc_hwmod_class, |
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.main_clk = "dss1_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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}, |
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}, |
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.flags = HWMOD_NO_IDLEST, |
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.dev_attr = &omap2_3_dss_dispc_dev_attr, |
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}; |
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static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
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{ .role = "ick", .clk = "dss_ick" }, |
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}; |
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struct omap_hwmod omap2xxx_dss_rfbi_hwmod = { |
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.name = "dss_rfbi", |
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.class = &omap2_rfbi_hwmod_class, |
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.main_clk = "dss1_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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}, |
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}, |
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.opt_clks = dss_rfbi_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), |
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.flags = HWMOD_NO_IDLEST, |
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}; |
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struct omap_hwmod omap2xxx_dss_venc_hwmod = { |
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.name = "dss_venc", |
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.class = &omap2_venc_hwmod_class, |
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.main_clk = "dss_54m_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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}, |
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}, |
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.flags = HWMOD_NO_IDLEST, |
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}; |
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/* gpio1 */ |
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struct omap_hwmod omap2xxx_gpio1_hwmod = { |
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.name = "gpio1", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.main_clk = "gpios_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = WKUP_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_gpio_hwmod_class, |
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}; |
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/* gpio2 */ |
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struct omap_hwmod omap2xxx_gpio2_hwmod = { |
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.name = "gpio2", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.main_clk = "gpios_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = WKUP_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_gpio_hwmod_class, |
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}; |
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/* gpio3 */ |
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struct omap_hwmod omap2xxx_gpio3_hwmod = { |
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.name = "gpio3", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.main_clk = "gpios_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = WKUP_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_gpio_hwmod_class, |
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}; |
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|
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/* gpio4 */ |
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struct omap_hwmod omap2xxx_gpio4_hwmod = { |
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.name = "gpio4", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.main_clk = "gpios_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = WKUP_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT, |
|
}, |
|
}, |
|
.class = &omap2xxx_gpio_hwmod_class, |
|
}; |
|
|
|
/* mcspi1 */ |
|
struct omap_hwmod omap2xxx_mcspi1_hwmod = { |
|
.name = "mcspi1", |
|
.main_clk = "mcspi1_fck", |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
.idlest_reg_id = 1, |
|
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT, |
|
}, |
|
}, |
|
.class = &omap2xxx_mcspi_class, |
|
}; |
|
|
|
/* mcspi2 */ |
|
struct omap_hwmod omap2xxx_mcspi2_hwmod = { |
|
.name = "mcspi2", |
|
.main_clk = "mcspi2_fck", |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
.idlest_reg_id = 1, |
|
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT, |
|
}, |
|
}, |
|
.class = &omap2xxx_mcspi_class, |
|
}; |
|
|
|
/* gpmc */ |
|
struct omap_hwmod omap2xxx_gpmc_hwmod = { |
|
.name = "gpmc", |
|
.class = &omap2xxx_gpmc_hwmod_class, |
|
.main_clk = "gpmc_fck", |
|
/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */ |
|
.flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS, |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
}, |
|
}, |
|
}; |
|
|
|
/* RNG */ |
|
|
|
static struct omap_hwmod_class_sysconfig omap2_rng_sysc = { |
|
.rev_offs = 0x3c, |
|
.sysc_offs = 0x40, |
|
.syss_offs = 0x44, |
|
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
|
SYSS_HAS_RESET_STATUS), |
|
.sysc_fields = &omap_hwmod_sysc_type1, |
|
}; |
|
|
|
static struct omap_hwmod_class omap2_rng_hwmod_class = { |
|
.name = "rng", |
|
.sysc = &omap2_rng_sysc, |
|
}; |
|
|
|
struct omap_hwmod omap2xxx_rng_hwmod = { |
|
.name = "rng", |
|
.main_clk = "l4_ck", |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
.idlest_reg_id = 4, |
|
.idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT, |
|
}, |
|
}, |
|
/* |
|
* XXX The first read from the SYSSTATUS register of the RNG |
|
* after the SYSCONFIG SOFTRESET bit is set triggers an |
|
* imprecise external abort. It's unclear why this happens. |
|
* Until this is analyzed, skip the IP block reset. |
|
*/ |
|
.flags = HWMOD_INIT_NO_RESET, |
|
.class = &omap2_rng_hwmod_class, |
|
}; |
|
|
|
/* SHAM */ |
|
|
|
static struct omap_hwmod_class_sysconfig omap2_sham_sysc = { |
|
.rev_offs = 0x5c, |
|
.sysc_offs = 0x60, |
|
.syss_offs = 0x64, |
|
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
|
SYSS_HAS_RESET_STATUS), |
|
.sysc_fields = &omap_hwmod_sysc_type1, |
|
}; |
|
|
|
static struct omap_hwmod_class omap2xxx_sham_class = { |
|
.name = "sham", |
|
.sysc = &omap2_sham_sysc, |
|
}; |
|
|
|
struct omap_hwmod omap2xxx_sham_hwmod = { |
|
.name = "sham", |
|
.main_clk = "l4_ck", |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
.idlest_reg_id = 4, |
|
.idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT, |
|
}, |
|
}, |
|
.class = &omap2xxx_sham_class, |
|
}; |
|
|
|
/* AES */ |
|
|
|
static struct omap_hwmod_class_sysconfig omap2_aes_sysc = { |
|
.rev_offs = 0x44, |
|
.sysc_offs = 0x48, |
|
.syss_offs = 0x4c, |
|
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
|
SYSS_HAS_RESET_STATUS), |
|
.sysc_fields = &omap_hwmod_sysc_type1, |
|
}; |
|
|
|
static struct omap_hwmod_class omap2xxx_aes_class = { |
|
.name = "aes", |
|
.sysc = &omap2_aes_sysc, |
|
}; |
|
|
|
struct omap_hwmod omap2xxx_aes_hwmod = { |
|
.name = "aes", |
|
.main_clk = "l4_ck", |
|
.prcm = { |
|
.omap2 = { |
|
.module_offs = CORE_MOD, |
|
.idlest_reg_id = 4, |
|
.idlest_idle_bit = OMAP24XX_ST_AES_SHIFT, |
|
}, |
|
}, |
|
.class = &omap2xxx_aes_class, |
|
};
|
|
|