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606 lines
15 KiB
606 lines
15 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips |
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* |
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* Copyright (C) 2009-2011 Nokia Corporation |
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* Copyright (C) 2012 Texas Instruments, Inc. |
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* Paul Walmsley |
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* |
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* XXX handle crossbar/shared link difference for L3? |
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* XXX these should be marked initdata for multi-OMAP kernels |
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*/ |
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|
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#include <linux/platform_data/i2c-omap.h> |
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#include <linux/platform_data/hsmmc-omap.h> |
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#include "omap_hwmod.h" |
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#include "l3_2xxx.h" |
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#include "soc.h" |
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#include "omap_hwmod_common_data.h" |
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#include "prm-regbits-24xx.h" |
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#include "cm-regbits-24xx.h" |
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#include "i2c.h" |
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#include "wd_timer.h" |
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|
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/* |
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* OMAP2430 hardware module integration data |
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* |
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* All of the data in this section should be autogeneratable from the |
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* TI hardware database or other technical documentation. Data that |
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* is driver-specific or driver-kernel integration-specific belongs |
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* elsewhere. |
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*/ |
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/* |
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* IP blocks |
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*/ |
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/* IVA2 (IVA2) */ |
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static struct omap_hwmod_rst_info omap2430_iva_resets[] = { |
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{ .name = "logic", .rst_shift = 0 }, |
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{ .name = "mmu", .rst_shift = 1 }, |
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}; |
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static struct omap_hwmod omap2430_iva_hwmod = { |
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.name = "iva", |
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.class = &iva_hwmod_class, |
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.clkdm_name = "dsp_clkdm", |
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.rst_lines = omap2430_iva_resets, |
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.rst_lines_cnt = ARRAY_SIZE(omap2430_iva_resets), |
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.main_clk = "dsp_fck", |
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}; |
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/* I2C common */ |
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static struct omap_hwmod_class_sysconfig i2c_sysc = { |
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.rev_offs = 0x00, |
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.sysc_offs = 0x20, |
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.syss_offs = 0x10, |
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.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE | |
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SYSS_HAS_RESET_STATUS), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class i2c_class = { |
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.name = "i2c", |
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.sysc = &i2c_sysc, |
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.reset = &omap_i2c_reset, |
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}; |
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/* I2C1 */ |
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static struct omap_hwmod omap2430_i2c1_hwmod = { |
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.name = "i2c1", |
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.flags = HWMOD_16BIT_REG, |
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.main_clk = "i2chs1_fck", |
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.prcm = { |
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.omap2 = { |
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/* |
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* NOTE: The CM_FCLKEN* and CM_ICLKEN* for |
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* I2CHS IP's do not follow the usual pattern. |
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* prcm_reg_id alone cannot be used to program |
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* the iclk and fclk. Needs to be handled using |
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* additional flags when clk handling is moved |
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* to hwmod framework. |
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*/ |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT, |
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}, |
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}, |
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.class = &i2c_class, |
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}; |
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/* I2C2 */ |
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static struct omap_hwmod omap2430_i2c2_hwmod = { |
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.name = "i2c2", |
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.flags = HWMOD_16BIT_REG, |
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.main_clk = "i2chs2_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT, |
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}, |
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}, |
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.class = &i2c_class, |
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}; |
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/* gpio5 */ |
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static struct omap_hwmod omap2430_gpio5_hwmod = { |
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.name = "gpio5", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.main_clk = "gpio5_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_gpio_hwmod_class, |
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}; |
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/* mailbox */ |
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static struct omap_hwmod omap2430_mailbox_hwmod = { |
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.name = "mailbox", |
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.class = &omap2xxx_mailbox_hwmod_class, |
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.main_clk = "mailboxes_ick", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
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}, |
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}, |
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}; |
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/* mcspi3 */ |
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static struct omap_hwmod omap2430_mcspi3_hwmod = { |
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.name = "mcspi3", |
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.main_clk = "mcspi3_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT, |
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}, |
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}, |
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.class = &omap2xxx_mcspi_class, |
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}; |
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/* usbhsotg */ |
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static struct omap_hwmod_class_sysconfig omap2430_usbhsotg_sysc = { |
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.rev_offs = 0x0400, |
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.sysc_offs = 0x0404, |
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.syss_offs = 0x0408, |
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.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE| |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
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SYSC_HAS_AUTOIDLE), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
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MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class usbotg_class = { |
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.name = "usbotg", |
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.sysc = &omap2430_usbhsotg_sysc, |
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}; |
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/* usb_otg_hs */ |
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static struct omap_hwmod omap2430_usbhsotg_hwmod = { |
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.name = "usb_otg_hs", |
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.main_clk = "usbhs_ick", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT, |
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}, |
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}, |
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.class = &usbotg_class, |
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/* |
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* Erratum ID: i479 idle_req / idle_ack mechanism potentially |
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* broken when autoidle is enabled |
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* workaround is to disable the autoidle bit at module level. |
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*/ |
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.flags = HWMOD_NO_OCP_AUTOIDLE | HWMOD_SWSUP_SIDLE |
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| HWMOD_SWSUP_MSTANDBY, |
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}; |
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/* |
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* 'mcbsp' class |
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* multi channel buffered serial port controller |
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*/ |
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static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = { |
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.rev_offs = 0x007C, |
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.sysc_offs = 0x008C, |
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.sysc_flags = (SYSC_HAS_SOFTRESET), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = { |
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.name = "mcbsp", |
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.sysc = &omap2430_mcbsp_sysc, |
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}; |
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static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = { |
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{ .role = "pad_fck", .clk = "mcbsp_clks" }, |
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{ .role = "prcm_fck", .clk = "func_96m_ck" }, |
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}; |
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/* mcbsp1 */ |
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static struct omap_hwmod omap2430_mcbsp1_hwmod = { |
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.name = "mcbsp1", |
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.class = &omap2430_mcbsp_hwmod_class, |
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.main_clk = "mcbsp1_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
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}, |
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}, |
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.opt_clks = mcbsp_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), |
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}; |
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/* mcbsp2 */ |
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static struct omap_hwmod omap2430_mcbsp2_hwmod = { |
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.name = "mcbsp2", |
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.class = &omap2430_mcbsp_hwmod_class, |
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.main_clk = "mcbsp2_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
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}, |
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}, |
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.opt_clks = mcbsp_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), |
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}; |
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/* mcbsp3 */ |
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static struct omap_hwmod omap2430_mcbsp3_hwmod = { |
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.name = "mcbsp3", |
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.class = &omap2430_mcbsp_hwmod_class, |
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.main_clk = "mcbsp3_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT, |
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}, |
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}, |
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.opt_clks = mcbsp_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), |
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}; |
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/* mcbsp4 */ |
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static struct omap_hwmod omap2430_mcbsp4_hwmod = { |
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.name = "mcbsp4", |
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.class = &omap2430_mcbsp_hwmod_class, |
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.main_clk = "mcbsp4_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT, |
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}, |
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}, |
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.opt_clks = mcbsp_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), |
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}; |
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/* mcbsp5 */ |
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static struct omap_hwmod omap2430_mcbsp5_hwmod = { |
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.name = "mcbsp5", |
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.class = &omap2430_mcbsp_hwmod_class, |
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.main_clk = "mcbsp5_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT, |
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}, |
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}, |
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.opt_clks = mcbsp_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(mcbsp_opt_clks), |
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}; |
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/* MMC/SD/SDIO common */ |
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static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = { |
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.rev_offs = 0x1fc, |
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.sysc_offs = 0x10, |
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.syss_offs = 0x14, |
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.sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
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SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
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SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS), |
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
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.sysc_fields = &omap_hwmod_sysc_type1, |
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}; |
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static struct omap_hwmod_class omap2430_mmc_class = { |
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.name = "mmc", |
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.sysc = &omap2430_mmc_sysc, |
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}; |
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/* MMC/SD/SDIO1 */ |
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static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = { |
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{ .role = "dbck", .clk = "mmchsdb1_fck" }, |
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}; |
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static struct omap_hsmmc_dev_attr mmc1_dev_attr = { |
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.flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
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}; |
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static struct omap_hwmod omap2430_mmc1_hwmod = { |
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.name = "mmc1", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.opt_clks = omap2430_mmc1_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks), |
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.main_clk = "mmchs1_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT, |
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}, |
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}, |
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.dev_attr = &mmc1_dev_attr, |
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.class = &omap2430_mmc_class, |
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}; |
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/* MMC/SD/SDIO2 */ |
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static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = { |
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{ .role = "dbck", .clk = "mmchsdb2_fck" }, |
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}; |
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static struct omap_hwmod omap2430_mmc2_hwmod = { |
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.name = "mmc2", |
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.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
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.opt_clks = omap2430_mmc2_opt_clks, |
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.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks), |
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.main_clk = "mmchs2_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 2, |
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.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT, |
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}, |
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}, |
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.class = &omap2430_mmc_class, |
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}; |
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/* HDQ1W/1-wire */ |
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static struct omap_hwmod omap2430_hdq1w_hwmod = { |
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.name = "hdq1w", |
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.main_clk = "hdq_fck", |
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.prcm = { |
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.omap2 = { |
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.module_offs = CORE_MOD, |
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.idlest_reg_id = 1, |
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.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT, |
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}, |
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}, |
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.class = &omap2_hdq1w_class, |
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}; |
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/* |
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* interfaces |
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*/ |
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/* L3 -> L4_CORE interface */ |
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/* l3_core -> usbhsotg interface */ |
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static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = { |
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.master = &omap2430_usbhsotg_hwmod, |
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.slave = &omap2xxx_l3_main_hwmod, |
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.clk = "core_l3_ck", |
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.user = OCP_USER_MPU, |
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}; |
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/* L4 CORE -> I2C1 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_i2c1_hwmod, |
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.clk = "i2c1_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* L4 CORE -> I2C2 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_i2c2_hwmod, |
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.clk = "i2c2_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_core ->usbhsotg interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_usbhsotg_hwmod, |
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.clk = "usb_l4_ick", |
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.user = OCP_USER_MPU, |
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}; |
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/* L4 CORE -> MMC1 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mmc1_hwmod, |
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.clk = "mmchs1_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* L4 CORE -> MMC2 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mmc2_hwmod, |
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.clk = "mmchs2_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4 core -> mcspi3 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcspi3_hwmod, |
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.clk = "mcspi3_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* IVA2 <- L3 interface */ |
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static struct omap_hwmod_ocp_if omap2430_l3__iva = { |
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.master = &omap2xxx_l3_main_hwmod, |
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.slave = &omap2430_iva_hwmod, |
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.clk = "core_l3_ck", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_wkup -> wd_timer2 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = { |
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.master = &omap2xxx_l4_wkup_hwmod, |
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.slave = &omap2xxx_wd_timer2_hwmod, |
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.clk = "mpu_wdt_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_wkup -> gpio1 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = { |
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.master = &omap2xxx_l4_wkup_hwmod, |
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.slave = &omap2xxx_gpio1_hwmod, |
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.clk = "gpios_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_wkup -> gpio2 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = { |
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.master = &omap2xxx_l4_wkup_hwmod, |
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.slave = &omap2xxx_gpio2_hwmod, |
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.clk = "gpios_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_wkup -> gpio3 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = { |
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.master = &omap2xxx_l4_wkup_hwmod, |
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.slave = &omap2xxx_gpio3_hwmod, |
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.clk = "gpios_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_wkup -> gpio4 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = { |
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.master = &omap2xxx_l4_wkup_hwmod, |
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.slave = &omap2xxx_gpio4_hwmod, |
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.clk = "gpios_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_core -> gpio5 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_gpio5_hwmod, |
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.clk = "gpio5_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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/* l4_core -> mailbox */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mailbox_hwmod, |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> mcbsp1 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcbsp1_hwmod, |
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.clk = "mcbsp1_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> mcbsp2 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcbsp2_hwmod, |
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.clk = "mcbsp2_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> mcbsp3 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcbsp3_hwmod, |
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.clk = "mcbsp3_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> mcbsp4 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcbsp4_hwmod, |
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.clk = "mcbsp4_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> mcbsp5 */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_mcbsp5_hwmod, |
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.clk = "mcbsp5_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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/* l4_core -> hdq1w */ |
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static struct omap_hwmod_ocp_if omap2430_l4_core__hdq1w = { |
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.master = &omap2xxx_l4_core_hwmod, |
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.slave = &omap2430_hdq1w_hwmod, |
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.clk = "hdq_ick", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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.flags = OMAP_FIREWALL_L4 | OCPIF_SWSUP_IDLE, |
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}; |
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|
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static struct omap_hwmod_ocp_if omap2430_l3__gpmc = { |
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.master = &omap2xxx_l3_main_hwmod, |
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.slave = &omap2xxx_gpmc_hwmod, |
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.clk = "core_l3_ck", |
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.user = OCP_USER_MPU | OCP_USER_SDMA, |
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}; |
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|
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static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = { |
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&omap2xxx_l3_main__l4_core, |
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&omap2xxx_mpu__l3_main, |
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&omap2xxx_dss__l3, |
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&omap2430_usbhsotg__l3, |
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&omap2430_l4_core__i2c1, |
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&omap2430_l4_core__i2c2, |
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&omap2xxx_l4_core__l4_wkup, |
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&omap2_l4_core__uart1, |
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&omap2_l4_core__uart2, |
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&omap2_l4_core__uart3, |
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&omap2430_l4_core__usbhsotg, |
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&omap2430_l4_core__mmc1, |
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&omap2430_l4_core__mmc2, |
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&omap2xxx_l4_core__mcspi1, |
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&omap2xxx_l4_core__mcspi2, |
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&omap2430_l4_core__mcspi3, |
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&omap2430_l3__iva, |
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&omap2xxx_l4_core__timer3, |
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&omap2xxx_l4_core__timer4, |
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&omap2xxx_l4_core__timer5, |
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&omap2xxx_l4_core__timer6, |
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&omap2xxx_l4_core__timer7, |
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&omap2xxx_l4_core__timer8, |
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&omap2xxx_l4_core__timer9, |
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&omap2xxx_l4_core__timer10, |
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&omap2xxx_l4_core__timer11, |
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&omap2xxx_l4_core__timer12, |
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&omap2430_l4_wkup__wd_timer2, |
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&omap2xxx_l4_core__dss, |
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&omap2xxx_l4_core__dss_dispc, |
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&omap2xxx_l4_core__dss_rfbi, |
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&omap2xxx_l4_core__dss_venc, |
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&omap2430_l4_wkup__gpio1, |
|
&omap2430_l4_wkup__gpio2, |
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&omap2430_l4_wkup__gpio3, |
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&omap2430_l4_wkup__gpio4, |
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&omap2430_l4_core__gpio5, |
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&omap2430_l4_core__mailbox, |
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&omap2430_l4_core__mcbsp1, |
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&omap2430_l4_core__mcbsp2, |
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&omap2430_l4_core__mcbsp3, |
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&omap2430_l4_core__mcbsp4, |
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&omap2430_l4_core__mcbsp5, |
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&omap2430_l4_core__hdq1w, |
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&omap2xxx_l4_core__rng, |
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&omap2xxx_l4_core__sham, |
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&omap2xxx_l4_core__aes, |
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&omap2430_l3__gpmc, |
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NULL, |
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}; |
|
|
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int __init omap2430_hwmod_init(void) |
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{ |
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omap_hwmod_init(); |
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return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs); |
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}
|
|
|