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133 lines
3.5 KiB
133 lines
3.5 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Secondary CPU startup routine source file. |
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* |
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* Copyright (C) 2009-2014 Texas Instruments, Inc. |
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* |
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* Author: |
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* Santosh Shilimkar <santosh.shilimkar@ti.com> |
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* |
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* Interface functions needed for the SMP. This file is based on arm |
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* realview smp platform. |
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* Copyright (c) 2003 ARM Limited. |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/init.h> |
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#include <asm/assembler.h> |
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#include "omap44xx.h" |
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/* Physical address needed since MMU not enabled yet on secondary core */ |
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#define AUX_CORE_BOOT0_PA 0x48281800 |
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#define API_HYP_ENTRY 0x102 |
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ENTRY(omap_secondary_startup) |
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#ifdef CONFIG_SMP |
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b secondary_startup |
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#else |
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/* Should never get here */ |
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again: wfi |
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b again |
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#endif |
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#ENDPROC(omap_secondary_startup) |
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/* |
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* OMAP5 specific entry point for secondary CPU to jump from ROM |
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* code. This routine also provides a holding flag into which |
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* secondary core is held until we're ready for it to initialise. |
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* The primary core will update this flag using a hardware |
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* register AuxCoreBoot0. |
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*/ |
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ENTRY(omap5_secondary_startup) |
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wait: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 |
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ldr r0, [r2] |
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mov r0, r0, lsr #5 |
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mrc p15, 0, r4, c0, c0, 5 |
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and r4, r4, #0x0f |
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cmp r0, r4 |
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bne wait |
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b omap_secondary_startup |
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ENDPROC(omap5_secondary_startup) |
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/* |
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* Same as omap5_secondary_startup except we call into the ROM to |
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* enable HYP mode first. This is called instead of |
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* omap5_secondary_startup if the primary CPU was put into HYP mode by |
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* the boot loader. |
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*/ |
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.arch armv7-a |
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.arch_extension sec |
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ENTRY(omap5_secondary_hyp_startup) |
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wait_2: ldr r2, =AUX_CORE_BOOT0_PA @ read from AuxCoreBoot0 |
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ldr r0, [r2] |
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mov r0, r0, lsr #5 |
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mrc p15, 0, r4, c0, c0, 5 |
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and r4, r4, #0x0f |
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cmp r0, r4 |
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bne wait_2 |
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ldr r12, =API_HYP_ENTRY |
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badr r0, hyp_boot |
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smc #0 |
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hyp_boot: |
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b omap_secondary_startup |
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ENDPROC(omap5_secondary_hyp_startup) |
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/* |
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* OMAP4 specific entry point for secondary CPU to jump from ROM |
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* code. This routine also provides a holding flag into which |
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* secondary core is held until we're ready for it to initialise. |
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* The primary core will update this flag using a hardware |
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* register AuxCoreBoot0. |
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*/ |
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ENTRY(omap4_secondary_startup) |
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hold: ldr r12,=0x103 |
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dsb |
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smc #0 @ read from AuxCoreBoot0 |
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mov r0, r0, lsr #9 |
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mrc p15, 0, r4, c0, c0, 5 |
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and r4, r4, #0x0f |
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cmp r0, r4 |
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bne hold |
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/* |
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* we've been released from the wait loop,secondary_stack |
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* should now contain the SVC stack for this core |
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*/ |
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b omap_secondary_startup |
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ENDPROC(omap4_secondary_startup) |
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ENTRY(omap4460_secondary_startup) |
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hold_2: ldr r12,=0x103 |
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dsb |
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smc #0 @ read from AuxCoreBoot0 |
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mov r0, r0, lsr #9 |
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mrc p15, 0, r4, c0, c0, 5 |
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and r4, r4, #0x0f |
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cmp r0, r4 |
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bne hold_2 |
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/* |
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* GIC distributor control register has changed between |
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* CortexA9 r1pX and r2pX. The Control Register secure |
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* banked version is now composed of 2 bits: |
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* bit 0 == Secure Enable |
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* bit 1 == Non-Secure Enable |
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* The Non-Secure banked register has not changed |
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* Because the ROM Code is based on the r1pX GIC, the CPU1 |
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* GIC restoration will cause a problem to CPU0 Non-Secure SW. |
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* The workaround must be: |
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* 1) Before doing the CPU1 wakeup, CPU0 must disable |
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* the GIC distributor |
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* 2) CPU1 must re-enable the GIC distributor on |
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* it's wakeup path. |
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*/ |
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ldr r1, =OMAP44XX_GIC_DIST_BASE |
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ldr r0, [r1] |
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orr r0, #1 |
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str r0, [r1] |
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/* |
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* we've been released from the wait loop,secondary_stack |
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* should now contain the SVC stack for this core |
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*/ |
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b omap_secondary_startup |
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ENDPROC(omap4460_secondary_startup)
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