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419 lines
9.7 KiB
419 lines
9.7 KiB
/* |
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* OMAP2plus display device setup / initialization. |
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* |
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* Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/ |
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* Senthilvadivu Guruswamy |
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* Sumit Semwal |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/string.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/delay.h> |
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#include <linux/of.h> |
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#include <linux/of_platform.h> |
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#include <linux/slab.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/platform_data/omapdss.h> |
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#include "omap_hwmod.h" |
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#include "omap_device.h" |
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#include "common.h" |
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#include "soc.h" |
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#include "iomap.h" |
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#include "control.h" |
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#include "display.h" |
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#include "prm.h" |
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#define DISPC_CONTROL 0x0040 |
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#define DISPC_CONTROL2 0x0238 |
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#define DISPC_CONTROL3 0x0848 |
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#define DISPC_IRQSTATUS 0x0018 |
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#define DSS_CONTROL 0x40 |
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#define DSS_SDI_CONTROL 0x44 |
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#define DSS_PLL_CONTROL 0x48 |
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#define LCD_EN_MASK (0x1 << 0) |
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#define DIGIT_EN_MASK (0x1 << 1) |
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#define FRAMEDONE_IRQ_SHIFT 0 |
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#define EVSYNC_EVEN_IRQ_SHIFT 2 |
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#define EVSYNC_ODD_IRQ_SHIFT 3 |
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#define FRAMEDONE2_IRQ_SHIFT 22 |
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#define FRAMEDONE3_IRQ_SHIFT 30 |
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#define FRAMEDONETV_IRQ_SHIFT 24 |
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/* |
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* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC |
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* reset before deciding that something has gone wrong |
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*/ |
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#define FRAMEDONE_IRQ_TIMEOUT 100 |
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#if defined(CONFIG_FB_OMAP2) |
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static struct platform_device omap_display_device = { |
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.name = "omapdss", |
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.id = -1, |
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.dev = { |
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.platform_data = NULL, |
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}, |
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}; |
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#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 |
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static struct regmap *omap4_dsi_mux_syscon; |
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static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) |
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{ |
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u32 enable_mask, enable_shift; |
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u32 pipd_mask, pipd_shift; |
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u32 reg; |
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int ret; |
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if (dsi_id == 0) { |
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enable_mask = OMAP4_DSI1_LANEENABLE_MASK; |
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enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; |
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pipd_mask = OMAP4_DSI1_PIPD_MASK; |
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pipd_shift = OMAP4_DSI1_PIPD_SHIFT; |
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} else if (dsi_id == 1) { |
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enable_mask = OMAP4_DSI2_LANEENABLE_MASK; |
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enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; |
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pipd_mask = OMAP4_DSI2_PIPD_MASK; |
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pipd_shift = OMAP4_DSI2_PIPD_SHIFT; |
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} else { |
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return -ENODEV; |
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} |
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ret = regmap_read(omap4_dsi_mux_syscon, |
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OMAP4_DSIPHY_SYSCON_OFFSET, |
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®); |
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if (ret) |
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return ret; |
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reg &= ~enable_mask; |
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reg &= ~pipd_mask; |
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reg |= (lanes << enable_shift) & enable_mask; |
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reg |= (lanes << pipd_shift) & pipd_mask; |
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regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg); |
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return 0; |
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} |
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static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) |
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{ |
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if (cpu_is_omap44xx()) |
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return omap4_dsi_mux_pads(dsi_id, lane_mask); |
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return 0; |
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} |
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static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) |
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{ |
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if (cpu_is_omap44xx()) |
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omap4_dsi_mux_pads(dsi_id, 0); |
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} |
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static enum omapdss_version __init omap_display_get_version(void) |
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{ |
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if (cpu_is_omap24xx()) |
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return OMAPDSS_VER_OMAP24xx; |
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else if (cpu_is_omap3630()) |
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return OMAPDSS_VER_OMAP3630; |
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else if (cpu_is_omap34xx()) { |
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if (soc_is_am35xx()) { |
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return OMAPDSS_VER_AM35xx; |
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} else { |
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if (omap_rev() < OMAP3430_REV_ES3_0) |
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return OMAPDSS_VER_OMAP34xx_ES1; |
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else |
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return OMAPDSS_VER_OMAP34xx_ES3; |
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} |
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} else if (omap_rev() == OMAP4430_REV_ES1_0) |
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return OMAPDSS_VER_OMAP4430_ES1; |
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else if (omap_rev() == OMAP4430_REV_ES2_0 || |
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omap_rev() == OMAP4430_REV_ES2_1 || |
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omap_rev() == OMAP4430_REV_ES2_2) |
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return OMAPDSS_VER_OMAP4430_ES2; |
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else if (cpu_is_omap44xx()) |
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return OMAPDSS_VER_OMAP4; |
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else if (soc_is_omap54xx()) |
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return OMAPDSS_VER_OMAP5; |
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else if (soc_is_am43xx()) |
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return OMAPDSS_VER_AM43xx; |
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else if (soc_is_dra7xx()) |
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return OMAPDSS_VER_DRA7xx; |
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else |
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return OMAPDSS_VER_UNKNOWN; |
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} |
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static int __init omapdss_init_fbdev(void) |
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{ |
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static struct omap_dss_board_info board_data = { |
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.dsi_enable_pads = omap_dsi_enable_pads, |
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.dsi_disable_pads = omap_dsi_disable_pads, |
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}; |
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struct device_node *node; |
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int r; |
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board_data.version = omap_display_get_version(); |
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if (board_data.version == OMAPDSS_VER_UNKNOWN) { |
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pr_err("DSS not supported on this SoC\n"); |
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return -ENODEV; |
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} |
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omap_display_device.dev.platform_data = &board_data; |
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r = platform_device_register(&omap_display_device); |
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if (r < 0) { |
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pr_err("Unable to register omapdss device\n"); |
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return r; |
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} |
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/* create vrfb device */ |
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r = omap_init_vrfb(); |
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if (r < 0) { |
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pr_err("Unable to register omapvrfb device\n"); |
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return r; |
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} |
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/* create FB device */ |
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r = omap_init_fb(); |
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if (r < 0) { |
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pr_err("Unable to register omapfb device\n"); |
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return r; |
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} |
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/* create V4L2 display device */ |
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r = omap_init_vout(); |
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if (r < 0) { |
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pr_err("Unable to register omap_vout device\n"); |
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return r; |
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} |
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/* add DSI info for omap4 */ |
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node = of_find_node_by_name(NULL, "omap4_padconf_global"); |
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if (node) |
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omap4_dsi_mux_syscon = syscon_node_to_regmap(node); |
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return 0; |
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} |
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static const char * const omapdss_compat_names[] __initconst = { |
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"ti,omap2-dss", |
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"ti,omap3-dss", |
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"ti,omap4-dss", |
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"ti,omap5-dss", |
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"ti,dra7-dss", |
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}; |
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static struct device_node * __init omapdss_find_dss_of_node(void) |
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{ |
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struct device_node *node; |
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int i; |
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for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) { |
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node = of_find_compatible_node(NULL, NULL, |
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omapdss_compat_names[i]); |
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if (node) |
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return node; |
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} |
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return NULL; |
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} |
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static int __init omapdss_init_of(void) |
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{ |
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int r; |
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struct device_node *node; |
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struct platform_device *pdev; |
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/* only create dss helper devices if dss is enabled in the .dts */ |
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node = omapdss_find_dss_of_node(); |
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if (!node) |
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return 0; |
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if (!of_device_is_available(node)) { |
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of_node_put(node); |
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return 0; |
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} |
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pdev = of_find_device_by_node(node); |
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if (!pdev) { |
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pr_err("Unable to find DSS platform device\n"); |
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return -ENODEV; |
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} |
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r = of_platform_populate(node, NULL, NULL, &pdev->dev); |
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if (r) { |
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pr_err("Unable to populate DSS submodule devices\n"); |
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put_device(&pdev->dev); |
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return r; |
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} |
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return omapdss_init_fbdev(); |
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} |
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omap_device_initcall(omapdss_init_of); |
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#endif /* CONFIG_FB_OMAP2 */ |
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static void dispc_disable_outputs(void) |
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{ |
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u32 v, irq_mask = 0; |
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bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; |
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int i; |
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struct omap_dss_dispc_dev_attr *da; |
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struct omap_hwmod *oh; |
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oh = omap_hwmod_lookup("dss_dispc"); |
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if (!oh) { |
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WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); |
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return; |
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} |
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if (!oh->dev_attr) { |
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pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); |
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return; |
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} |
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da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; |
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/* store value of LCDENABLE and DIGITENABLE bits */ |
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v = omap_hwmod_read(oh, DISPC_CONTROL); |
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lcd_en = v & LCD_EN_MASK; |
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digit_en = v & DIGIT_EN_MASK; |
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/* store value of LCDENABLE for LCD2 */ |
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if (da->manager_count > 2) { |
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v = omap_hwmod_read(oh, DISPC_CONTROL2); |
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lcd2_en = v & LCD_EN_MASK; |
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} |
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/* store value of LCDENABLE for LCD3 */ |
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if (da->manager_count > 3) { |
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v = omap_hwmod_read(oh, DISPC_CONTROL3); |
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lcd3_en = v & LCD_EN_MASK; |
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} |
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if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) |
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return; /* no managers currently enabled */ |
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/* |
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* If any manager was enabled, we need to disable it before |
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* DSS clocks are disabled or DISPC module is reset |
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*/ |
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if (lcd_en) |
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irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; |
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if (digit_en) { |
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if (da->has_framedonetv_irq) { |
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irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; |
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} else { |
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irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | |
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1 << EVSYNC_ODD_IRQ_SHIFT; |
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} |
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} |
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if (lcd2_en) |
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irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; |
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if (lcd3_en) |
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irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; |
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/* |
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* clear any previous FRAMEDONE, FRAMEDONETV, |
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* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts |
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*/ |
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omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); |
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/* disable LCD and TV managers */ |
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v = omap_hwmod_read(oh, DISPC_CONTROL); |
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v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); |
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omap_hwmod_write(v, oh, DISPC_CONTROL); |
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/* disable LCD2 manager */ |
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if (da->manager_count > 2) { |
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v = omap_hwmod_read(oh, DISPC_CONTROL2); |
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v &= ~LCD_EN_MASK; |
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omap_hwmod_write(v, oh, DISPC_CONTROL2); |
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} |
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/* disable LCD3 manager */ |
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if (da->manager_count > 3) { |
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v = omap_hwmod_read(oh, DISPC_CONTROL3); |
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v &= ~LCD_EN_MASK; |
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omap_hwmod_write(v, oh, DISPC_CONTROL3); |
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} |
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i = 0; |
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while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != |
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irq_mask) { |
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i++; |
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if (i > FRAMEDONE_IRQ_TIMEOUT) { |
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pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); |
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break; |
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} |
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mdelay(1); |
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} |
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} |
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int omap_dss_reset(struct omap_hwmod *oh) |
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{ |
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struct omap_hwmod_opt_clk *oc; |
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int c = 0; |
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int i, r; |
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if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { |
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pr_err("dss_core: hwmod data doesn't contain reset data\n"); |
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return -EINVAL; |
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} |
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for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) |
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clk_prepare_enable(oc->_clk); |
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dispc_disable_outputs(); |
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/* clear SDI registers */ |
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if (cpu_is_omap3430()) { |
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omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); |
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omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); |
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} |
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/* |
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* clear DSS_CONTROL register to switch DSS clock sources to |
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* PRCM clock, if any |
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*/ |
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omap_hwmod_write(0x0, oh, DSS_CONTROL); |
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omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) |
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& SYSS_RESETDONE_MASK), |
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MAX_MODULE_SOFTRESET_WAIT, c); |
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if (c == MAX_MODULE_SOFTRESET_WAIT) |
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pr_warn("dss_core: waiting for reset to finish failed\n"); |
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else |
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pr_debug("dss_core: softreset done\n"); |
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for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) |
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clk_disable_unprepare(oc->_clk); |
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r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; |
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return r; |
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}
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