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255 lines
6.6 KiB
255 lines
6.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* OMAP2xxx DVFS virtual clock functions |
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* |
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* Copyright (C) 2005-2008, 2012 Texas Instruments, Inc. |
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* Copyright (C) 2004-2010 Nokia Corporation |
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* |
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* Contacts: |
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* Richard Woodruff <[email protected]> |
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* Paul Walmsley |
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* |
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* Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
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* Gordon McNutt and RidgeRun, Inc. |
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* |
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* XXX Some of this code should be replaceable by the upcoming OPP layer |
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* code. However, some notion of "rate set" is probably still necessary |
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* for OMAP2xxx at least. Rate sets should be generalized so they can be |
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* used for any OMAP chip, not just OMAP2xxx. In particular, Richard Woodruff |
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* has in the past expressed a preference to use rate sets for OPP changes, |
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* rather than dynamically recalculating the clock tree, so if someone wants |
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* this badly enough to write the code to handle it, we should support it |
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* as an option. |
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*/ |
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#undef DEBUG |
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#include <linux/kernel.h> |
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#include <linux/errno.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/cpufreq.h> |
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#include <linux/slab.h> |
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#include "soc.h" |
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#include "clock.h" |
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#include "clock2xxx.h" |
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#include "opp2xxx.h" |
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#include "cm2xxx.h" |
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#include "cm-regbits-24xx.h" |
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#include "sdrc.h" |
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#include "sram.h" |
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const struct prcm_config *curr_prcm_set; |
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const struct prcm_config *rate_table; |
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/* |
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* sys_ck_rate: the rate of the external high-frequency clock |
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* oscillator on the board. Set by the SoC-specific clock init code. |
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* Once set during a boot, will not change. |
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*/ |
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static unsigned long sys_ck_rate; |
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/** |
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* omap2_table_mpu_recalc - just return the MPU speed |
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* @clk: virt_prcm_set struct clk |
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* |
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* Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. |
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*/ |
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unsigned long omap2_table_mpu_recalc(struct clk_hw *clk, |
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unsigned long parent_rate) |
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{ |
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return curr_prcm_set->mpu_speed; |
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} |
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/* |
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* Look for a rate equal or less than the target rate given a configuration set. |
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* |
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* What's not entirely clear is "which" field represents the key field. |
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* Some might argue L3-DDR, others ARM, others IVA. This code is simple and |
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* just uses the ARM rates. |
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*/ |
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long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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const struct prcm_config *ptr; |
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long highest_rate; |
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highest_rate = -EINVAL; |
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for (ptr = rate_table; ptr->mpu_speed; ptr++) { |
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if (!(ptr->flags & cpu_mask)) |
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continue; |
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if (ptr->xtal_speed != sys_ck_rate) |
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continue; |
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highest_rate = ptr->mpu_speed; |
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/* Can check only after xtal frequency check */ |
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if (ptr->mpu_speed <= rate) |
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break; |
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} |
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return highest_rate; |
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} |
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/* Sets basic clocks based on the specified rate */ |
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int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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u32 cur_rate, done_rate, bypass = 0; |
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const struct prcm_config *prcm; |
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unsigned long found_speed = 0; |
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unsigned long flags; |
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for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
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if (!(prcm->flags & cpu_mask)) |
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continue; |
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if (prcm->xtal_speed != sys_ck_rate) |
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continue; |
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if (prcm->mpu_speed <= rate) { |
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found_speed = prcm->mpu_speed; |
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break; |
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} |
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} |
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if (!found_speed) { |
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printk(KERN_INFO "Could not set MPU rate to %luMHz\n", |
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rate / 1000000); |
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return -EINVAL; |
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} |
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curr_prcm_set = prcm; |
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cur_rate = omap2xxx_clk_get_core_rate(); |
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if (prcm->dpll_speed == cur_rate / 2) { |
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
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} else if (prcm->dpll_speed == cur_rate * 2) { |
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
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} else if (prcm->dpll_speed != cur_rate) { |
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local_irq_save(flags); |
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if (prcm->dpll_speed == prcm->xtal_speed) |
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bypass = 1; |
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if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
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CORE_CLK_SRC_DPLL_X2) |
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done_rate = CORE_CLK_SRC_DPLL_X2; |
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else |
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done_rate = CORE_CLK_SRC_DPLL; |
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omap2xxx_cm_set_mod_dividers(prcm->cm_clksel_mpu, |
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prcm->cm_clksel_dsp, |
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prcm->cm_clksel_gfx, |
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prcm->cm_clksel1_core, |
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prcm->cm_clksel_mdm); |
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/* x2 to enter omap2xxx_sdrc_init_params() */ |
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omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
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omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, |
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bypass); |
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omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
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omap2xxx_sdrc_reprogram(done_rate, 0); |
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local_irq_restore(flags); |
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} |
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return 0; |
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} |
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/** |
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* omap2xxx_clkt_vps_check_bootloader_rate - determine which of the rate |
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* table sets matches the current CORE DPLL hardware rate |
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* |
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* Check the MPU rate set by bootloader. Sets the 'curr_prcm_set' |
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* global to point to the active rate set when found; otherwise, sets |
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* it to NULL. No return value; |
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*/ |
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void omap2xxx_clkt_vps_check_bootloader_rates(void) |
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{ |
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const struct prcm_config *prcm = NULL; |
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unsigned long rate; |
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rate = omap2xxx_clk_get_core_rate(); |
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for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
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if (!(prcm->flags & cpu_mask)) |
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continue; |
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if (prcm->xtal_speed != sys_ck_rate) |
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continue; |
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if (prcm->dpll_speed <= rate) |
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break; |
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} |
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curr_prcm_set = prcm; |
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} |
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/** |
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* omap2xxx_clkt_vps_late_init - store a copy of the sys_ck rate |
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* |
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* Store a copy of the sys_ck rate for later use by the OMAP2xxx DVFS |
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* code. (The sys_ck rate does not -- or rather, must not -- change |
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* during kernel runtime.) Must be called after we have a valid |
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* sys_ck rate, but before the virt_prcm_set clock rate is |
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* recalculated. No return value. |
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*/ |
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void omap2xxx_clkt_vps_late_init(void) |
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{ |
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struct clk *c; |
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c = clk_get(NULL, "sys_ck"); |
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if (IS_ERR(c)) { |
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WARN(1, "could not locate sys_ck\n"); |
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} else { |
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sys_ck_rate = clk_get_rate(c); |
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clk_put(c); |
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} |
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} |
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#ifdef CONFIG_OF |
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#include <linux/clk-provider.h> |
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#include <linux/clkdev.h> |
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static const struct clk_ops virt_prcm_set_ops = { |
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.recalc_rate = &omap2_table_mpu_recalc, |
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.set_rate = &omap2_select_table_rate, |
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.round_rate = &omap2_round_to_table_rate, |
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}; |
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/** |
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* omap2xxx_clkt_vps_init - initialize virt_prcm_set clock |
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* |
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* Does a manual init for the virtual prcm DVFS clock for OMAP2. This |
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* function is called only from omap2 DT clock init, as the virtual |
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* node is not modelled in the DT clock data. |
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*/ |
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void omap2xxx_clkt_vps_init(void) |
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{ |
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struct clk_init_data init = { NULL }; |
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struct clk_hw_omap *hw = NULL; |
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struct clk *clk; |
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const char *parent_name = "mpu_ck"; |
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omap2xxx_clkt_vps_late_init(); |
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omap2xxx_clkt_vps_check_bootloader_rates(); |
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hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
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if (!hw) |
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return; |
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init.name = "virt_prcm_set"; |
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init.ops = &virt_prcm_set_ops; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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hw->hw.init = &init; |
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clk = clk_register(NULL, &hw->hw); |
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if (IS_ERR(clk)) { |
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printk(KERN_ERR "Failed to register clock\n"); |
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kfree(hw); |
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return; |
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} |
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clkdev_create(clk, "cpufreq_ck", NULL); |
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} |
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#endif
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