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276 lines
7.9 KiB
276 lines
7.9 KiB
/* |
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* linux/arch/arm/mach-omap1/irq.c |
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* |
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* Interrupt handler for all OMAP boards |
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* |
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* Copyright (C) 2004 Nokia Corporation |
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* Written by Tony Lindgren <[email protected]> |
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* Major cleanups by Juha Yrjölä <[email protected]> |
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* |
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* Completely re-written to support various OMAP chips with bank specific |
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* interrupt handlers. |
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* |
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* Some snippets of the code taken from the older OMAP interrupt handler |
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* Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <[email protected]> |
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* |
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* GPIO interrupt handler moved to gpio.c by Juha Yrjola |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/gpio.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/sched.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <asm/irq.h> |
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#include <asm/exception.h> |
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#include <asm/mach/irq.h> |
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#include "soc.h" |
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#include <mach/hardware.h> |
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#include "common.h" |
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#define IRQ_BANK(irq) ((irq) >> 5) |
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#define IRQ_BIT(irq) ((irq) & 0x1f) |
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struct omap_irq_bank { |
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unsigned long base_reg; |
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void __iomem *va; |
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unsigned long trigger_map; |
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unsigned long wake_enable; |
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}; |
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static u32 omap_l2_irq; |
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static unsigned int irq_bank_count; |
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static struct omap_irq_bank *irq_banks; |
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static struct irq_domain *domain; |
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static inline unsigned int irq_bank_readl(int bank, int offset) |
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{ |
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return readl_relaxed(irq_banks[bank].va + offset); |
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} |
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static inline void irq_bank_writel(unsigned long value, int bank, int offset) |
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{ |
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writel_relaxed(value, irq_banks[bank].va + offset); |
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} |
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static void omap_ack_irq(int irq) |
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{ |
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if (irq > 31) |
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writel_relaxed(0x1, irq_banks[1].va + IRQ_CONTROL_REG_OFFSET); |
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writel_relaxed(0x1, irq_banks[0].va + IRQ_CONTROL_REG_OFFSET); |
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} |
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static void omap_mask_ack_irq(struct irq_data *d) |
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{ |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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ct->chip.irq_mask(d); |
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omap_ack_irq(d->irq); |
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} |
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/* |
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* Allows tuning the IRQ type and priority |
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* |
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* NOTE: There is currently no OMAP fiq handler for Linux. Read the |
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* mailing list threads on FIQ handlers if you are planning to |
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* add a FIQ handler for OMAP. |
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*/ |
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static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) |
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{ |
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signed int bank; |
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unsigned long val, offset; |
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bank = IRQ_BANK(irq); |
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/* FIQ is only available on bank 0 interrupts */ |
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fiq = bank ? 0 : (fiq & 0x1); |
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val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); |
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offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4; |
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irq_bank_writel(val, bank, offset); |
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} |
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#if defined (CONFIG_ARCH_OMAP730) || defined (CONFIG_ARCH_OMAP850) |
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static struct omap_irq_bank omap7xx_irq_banks[] = { |
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3f8e22f }, |
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb9c1f2 }, |
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0x800040f3 }, |
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}; |
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#endif |
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#ifdef CONFIG_ARCH_OMAP15XX |
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static struct omap_irq_bank omap1510_irq_banks[] = { |
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3febfff }, |
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xffbfffed }, |
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}; |
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static struct omap_irq_bank omap310_irq_banks[] = { |
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3faefc3 }, |
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0x65b3c061 }, |
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}; |
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#endif |
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#if defined(CONFIG_ARCH_OMAP16XX) |
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static struct omap_irq_bank omap1610_irq_banks[] = { |
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{ .base_reg = OMAP_IH1_BASE, .trigger_map = 0xb3fefe8f }, |
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{ .base_reg = OMAP_IH2_BASE, .trigger_map = 0xfdb7c1fd }, |
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{ .base_reg = OMAP_IH2_BASE + 0x100, .trigger_map = 0xffffb7ff }, |
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{ .base_reg = OMAP_IH2_BASE + 0x200, .trigger_map = 0xffffffff }, |
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}; |
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#endif |
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asmlinkage void __exception_irq_entry omap1_handle_irq(struct pt_regs *regs) |
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{ |
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void __iomem *l1 = irq_banks[0].va; |
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void __iomem *l2 = irq_banks[1].va; |
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u32 irqnr; |
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do { |
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irqnr = readl_relaxed(l1 + IRQ_ITR_REG_OFFSET); |
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irqnr &= ~(readl_relaxed(l1 + IRQ_MIR_REG_OFFSET) & 0xffffffff); |
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if (!irqnr) |
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break; |
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irqnr = readl_relaxed(l1 + IRQ_SIR_FIQ_REG_OFFSET); |
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if (irqnr) |
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goto irq; |
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irqnr = readl_relaxed(l1 + IRQ_SIR_IRQ_REG_OFFSET); |
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if (irqnr == omap_l2_irq) { |
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irqnr = readl_relaxed(l2 + IRQ_SIR_IRQ_REG_OFFSET); |
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if (irqnr) |
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irqnr += 32; |
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} |
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irq: |
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if (irqnr) |
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handle_domain_irq(domain, irqnr, regs); |
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else |
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break; |
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} while (irqnr); |
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} |
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static __init void |
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omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) |
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{ |
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struct irq_chip_generic *gc; |
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struct irq_chip_type *ct; |
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gc = irq_alloc_generic_chip("MPU", 1, irq_start, base, |
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handle_level_irq); |
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ct = gc->chip_types; |
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ct->chip.irq_ack = omap_mask_ack_irq; |
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ct->chip.irq_mask = irq_gc_mask_set_bit; |
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ct->chip.irq_unmask = irq_gc_mask_clr_bit; |
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ct->chip.irq_set_wake = irq_gc_set_wake; |
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ct->regs.mask = IRQ_MIR_REG_OFFSET; |
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irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, |
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IRQ_NOREQUEST | IRQ_NOPROBE, 0); |
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} |
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void __init omap1_init_irq(void) |
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{ |
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struct irq_chip_type *ct; |
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struct irq_data *d = NULL; |
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int i, j, irq_base; |
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unsigned long nr_irqs; |
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#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
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if (cpu_is_omap7xx()) { |
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irq_banks = omap7xx_irq_banks; |
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irq_bank_count = ARRAY_SIZE(omap7xx_irq_banks); |
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} |
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#endif |
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#ifdef CONFIG_ARCH_OMAP15XX |
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if (cpu_is_omap1510()) { |
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irq_banks = omap1510_irq_banks; |
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irq_bank_count = ARRAY_SIZE(omap1510_irq_banks); |
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} |
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if (cpu_is_omap310()) { |
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irq_banks = omap310_irq_banks; |
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irq_bank_count = ARRAY_SIZE(omap310_irq_banks); |
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} |
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#endif |
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#if defined(CONFIG_ARCH_OMAP16XX) |
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if (cpu_is_omap16xx()) { |
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irq_banks = omap1610_irq_banks; |
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irq_bank_count = ARRAY_SIZE(omap1610_irq_banks); |
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} |
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#endif |
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for (i = 0; i < irq_bank_count; i++) { |
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irq_banks[i].va = ioremap(irq_banks[i].base_reg, 0xff); |
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if (WARN_ON(!irq_banks[i].va)) |
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return; |
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} |
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nr_irqs = irq_bank_count * 32; |
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); |
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if (irq_base < 0) { |
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pr_warn("Couldn't allocate IRQ numbers\n"); |
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irq_base = 0; |
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} |
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omap_l2_irq = cpu_is_omap7xx() ? irq_base + 1 : irq_base; |
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omap_l2_irq -= NR_IRQS_LEGACY; |
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domain = irq_domain_add_legacy(NULL, nr_irqs, irq_base, 0, |
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&irq_domain_simple_ops, NULL); |
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pr_info("Total of %lu interrupts in %i interrupt banks\n", |
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nr_irqs, irq_bank_count); |
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/* Mask and clear all interrupts */ |
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for (i = 0; i < irq_bank_count; i++) { |
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irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET); |
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irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET); |
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} |
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/* Clear any pending interrupts */ |
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irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET); |
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irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET); |
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/* Enable interrupts in global mask */ |
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if (cpu_is_omap7xx()) |
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irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET); |
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/* Install the interrupt handlers for each bank */ |
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for (i = 0; i < irq_bank_count; i++) { |
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for (j = i * 32; j < (i + 1) * 32; j++) { |
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int irq_trigger; |
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irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); |
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omap_irq_set_cfg(j, 0, 0, irq_trigger); |
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irq_clear_status_flags(j, IRQ_NOREQUEST); |
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} |
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omap_alloc_gc(irq_banks[i].va, irq_base + i * 32, 32); |
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} |
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/* Unmask level 2 handler */ |
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d = irq_get_irq_data(irq_find_mapping(domain, omap_l2_irq)); |
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if (d) { |
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ct = irq_data_get_chip_type(d); |
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ct->chip.irq_unmask(d); |
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} |
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}
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