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288 lines
10 KiB
288 lines
10 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* linux/arch/arm/mach-omap1/clock.h |
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* |
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* Copyright (C) 2004 - 2005, 2009 Nokia corporation |
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* Written by Tuukka Tikkanen <[email protected]> |
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* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc |
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*/ |
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#ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H |
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#define __ARCH_ARM_MACH_OMAP1_CLOCK_H |
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#include <linux/clk.h> |
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#include <linux/list.h> |
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#include <linux/clkdev.h> |
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struct module; |
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struct clk; |
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struct omap_clk { |
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u16 cpu; |
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struct clk_lookup lk; |
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}; |
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#define CLK(dev, con, ck, cp) \ |
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{ \ |
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.cpu = cp, \ |
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.lk = { \ |
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.dev_id = dev, \ |
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.con_id = con, \ |
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.clk = ck, \ |
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}, \ |
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} |
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/* Platform flags for the clkdev-OMAP integration code */ |
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#define CK_310 (1 << 0) |
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#define CK_7XX (1 << 1) /* 7xx, 850 */ |
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#define CK_1510 (1 << 2) |
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#define CK_16XX (1 << 3) /* 16xx, 17xx, 5912 */ |
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#define CK_1710 (1 << 4) /* 1710 extra for rate selection */ |
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/* Temporary, needed during the common clock framework conversion */ |
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#define __clk_get_name(clk) (clk->name) |
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#define __clk_get_parent(clk) (clk->parent) |
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#define __clk_get_rate(clk) (clk->rate) |
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/** |
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* struct clkops - some clock function pointers |
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* @enable: fn ptr that enables the current clock in hardware |
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* @disable: fn ptr that enables the current clock in hardware |
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* @find_idlest: function returning the IDLEST register for the clock's IP blk |
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* @find_companion: function returning the "companion" clk reg for the clock |
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* @allow_idle: fn ptr that enables autoidle for the current clock in hardware |
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* @deny_idle: fn ptr that disables autoidle for the current clock in hardware |
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* |
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* A "companion" clk is an accompanying clock to the one being queried |
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* that must be enabled for the IP module connected to the clock to |
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* become accessible by the hardware. Neither @find_idlest nor |
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* @find_companion should be needed; that information is IP |
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* block-specific; the hwmod code has been created to handle this, but |
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* until hwmod data is ready and drivers have been converted to use PM |
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* runtime calls in place of clk_enable()/clk_disable(), @find_idlest and |
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* @find_companion must, unfortunately, remain. |
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*/ |
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struct clkops { |
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int (*enable)(struct clk *); |
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void (*disable)(struct clk *); |
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void (*find_idlest)(struct clk *, void __iomem **, |
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u8 *, u8 *); |
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void (*find_companion)(struct clk *, void __iomem **, |
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u8 *); |
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void (*allow_idle)(struct clk *); |
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void (*deny_idle)(struct clk *); |
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}; |
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/* |
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* struct clk.flags possibilities |
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* |
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* XXX document the rest of the clock flags here |
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* |
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* CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL |
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* bits share the same register. This flag allows the |
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* omap4_dpllmx*() code to determine which GATE_CTRL bit field |
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* should be used. This is a temporary solution - a better approach |
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* would be to associate clock type-specific data with the clock, |
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* similar to the struct dpll_data approach. |
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*/ |
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#define ENABLE_REG_32BIT (1 << 0) /* Use 32-bit access */ |
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#define CLOCK_IDLE_CONTROL (1 << 1) |
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#define CLOCK_NO_IDLE_PARENT (1 << 2) |
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#define ENABLE_ON_INIT (1 << 3) /* Enable upon framework init */ |
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#define INVERT_ENABLE (1 << 4) /* 0 enables, 1 disables */ |
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#define CLOCK_CLKOUTX2 (1 << 5) |
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/** |
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* struct clk - OMAP struct clk |
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* @node: list_head connecting this clock into the full clock list |
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* @ops: struct clkops * for this clock |
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* @name: the name of the clock in the hardware (used in hwmod data and debug) |
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* @parent: pointer to this clock's parent struct clk |
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* @children: list_head connecting to the child clks' @sibling list_heads |
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* @sibling: list_head connecting this clk to its parent clk's @children |
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* @rate: current clock rate |
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* @enable_reg: register to write to enable the clock (see @enable_bit) |
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* @recalc: fn ptr that returns the clock's current rate |
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* @set_rate: fn ptr that can change the clock's current rate |
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* @round_rate: fn ptr that can round the clock's current rate |
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* @init: fn ptr to do clock-specific initialization |
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* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg) |
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* @usecount: number of users that have requested this clock to be enabled |
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* @fixed_div: when > 0, this clock's rate is its parent's rate / @fixed_div |
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* @flags: see "struct clk.flags possibilities" above |
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* @rate_offset: bitshift for rate selection bitfield (OMAP1 only) |
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* @src_offset: bitshift for source selection bitfield (OMAP1 only) |
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* |
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* XXX @rate_offset, @src_offset should probably be removed and OMAP1 |
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* clock code converted to use clksel. |
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* |
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* XXX @usecount is poorly named. It should be "enable_count" or |
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* something similar. "users" in the description refers to kernel |
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* code (core code or drivers) that have called clk_enable() and not |
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* yet called clk_disable(); the usecount of parent clocks is also |
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* incremented by the clock code when clk_enable() is called on child |
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* clocks and decremented by the clock code when clk_disable() is |
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* called on child clocks. |
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* |
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* XXX @clkdm, @usecount, @children, @sibling should be marked for |
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* internal use only. |
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* |
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* @children and @sibling are used to optimize parent-to-child clock |
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* tree traversals. (child-to-parent traversals use @parent.) |
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* |
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* XXX The notion of the clock's current rate probably needs to be |
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* separated from the clock's target rate. |
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*/ |
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struct clk { |
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struct list_head node; |
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const struct clkops *ops; |
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const char *name; |
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struct clk *parent; |
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struct list_head children; |
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struct list_head sibling; /* node for children */ |
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unsigned long rate; |
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void __iomem *enable_reg; |
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unsigned long (*recalc)(struct clk *); |
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int (*set_rate)(struct clk *, unsigned long); |
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long (*round_rate)(struct clk *, unsigned long); |
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void (*init)(struct clk *); |
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u8 enable_bit; |
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s8 usecount; |
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u8 fixed_div; |
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u8 flags; |
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u8 rate_offset; |
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u8 src_offset; |
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#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) |
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struct dentry *dent; /* For visible tree hierarchy */ |
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#endif |
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}; |
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struct clk_functions { |
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int (*clk_enable)(struct clk *clk); |
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void (*clk_disable)(struct clk *clk); |
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long (*clk_round_rate)(struct clk *clk, unsigned long rate); |
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int (*clk_set_rate)(struct clk *clk, unsigned long rate); |
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int (*clk_set_parent)(struct clk *clk, struct clk *parent); |
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void (*clk_allow_idle)(struct clk *clk); |
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void (*clk_deny_idle)(struct clk *clk); |
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void (*clk_disable_unused)(struct clk *clk); |
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}; |
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extern int clk_init(struct clk_functions *custom_clocks); |
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extern void clk_preinit(struct clk *clk); |
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extern int clk_register(struct clk *clk); |
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extern void clk_reparent(struct clk *child, struct clk *parent); |
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extern void clk_unregister(struct clk *clk); |
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extern void propagate_rate(struct clk *clk); |
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extern void recalculate_root_clocks(void); |
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extern unsigned long followparent_recalc(struct clk *clk); |
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extern void clk_enable_init_clocks(void); |
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unsigned long omap_fixed_divisor_recalc(struct clk *clk); |
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extern struct clk *omap_clk_get_by_name(const char *name); |
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extern int omap_clk_enable_autoidle_all(void); |
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extern int omap_clk_disable_autoidle_all(void); |
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extern const struct clkops clkops_null; |
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extern struct clk dummy_ck; |
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int omap1_clk_init(void); |
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void omap1_clk_late_init(void); |
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extern int omap1_clk_enable(struct clk *clk); |
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extern void omap1_clk_disable(struct clk *clk); |
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extern long omap1_clk_round_rate(struct clk *clk, unsigned long rate); |
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extern int omap1_clk_set_rate(struct clk *clk, unsigned long rate); |
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extern unsigned long omap1_ckctl_recalc(struct clk *clk); |
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extern int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
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extern unsigned long omap1_sossi_recalc(struct clk *clk); |
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extern unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); |
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extern int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate); |
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extern int omap1_set_uart_rate(struct clk *clk, unsigned long rate); |
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extern unsigned long omap1_uart_recalc(struct clk *clk); |
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extern int omap1_set_ext_clk_rate(struct clk *clk, unsigned long rate); |
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extern long omap1_round_ext_clk_rate(struct clk *clk, unsigned long rate); |
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extern void omap1_init_ext_clk(struct clk *clk); |
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extern int omap1_select_table_rate(struct clk *clk, unsigned long rate); |
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extern long omap1_round_to_table_rate(struct clk *clk, unsigned long rate); |
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extern int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
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extern long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
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extern unsigned long omap1_watchdog_recalc(struct clk *clk); |
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#ifdef CONFIG_OMAP_RESET_CLOCKS |
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extern void omap1_clk_disable_unused(struct clk *clk); |
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#else |
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#define omap1_clk_disable_unused NULL |
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#endif |
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struct uart_clk { |
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struct clk clk; |
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unsigned long sysc_addr; |
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}; |
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/* Provide a method for preventing idling some ARM IDLECT clocks */ |
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struct arm_idlect1_clk { |
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struct clk clk; |
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unsigned long no_idle_count; |
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__u8 idlect_shift; |
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}; |
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/* ARM_CKCTL bit shifts */ |
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#define CKCTL_PERDIV_OFFSET 0 |
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#define CKCTL_LCDDIV_OFFSET 2 |
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#define CKCTL_ARMDIV_OFFSET 4 |
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#define CKCTL_DSPDIV_OFFSET 6 |
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#define CKCTL_TCDIV_OFFSET 8 |
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#define CKCTL_DSPMMUDIV_OFFSET 10 |
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/*#define ARM_TIMXO 12*/ |
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#define EN_DSPCK 13 |
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/*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ |
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/* DSP_CKCTL bit shifts */ |
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#define CKCTL_DSPPERDIV_OFFSET 0 |
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/* ARM_IDLECT2 bit shifts */ |
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#define EN_WDTCK 0 |
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#define EN_XORPCK 1 |
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#define EN_PERCK 2 |
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#define EN_LCDCK 3 |
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#define EN_LBCK 4 /* Not on 1610/1710 */ |
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/*#define EN_HSABCK 5*/ |
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#define EN_APICK 6 |
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#define EN_TIMCK 7 |
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#define DMACK_REQ 8 |
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#define EN_GPIOCK 9 /* Not on 1610/1710 */ |
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/*#define EN_LBFREECK 10*/ |
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#define EN_CKOUT_ARM 11 |
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/* ARM_IDLECT3 bit shifts */ |
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#define EN_OCPI_CK 0 |
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#define EN_TC1_CK 2 |
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#define EN_TC2_CK 4 |
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/* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ |
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#define EN_DSPTIMCK 5 |
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/* Various register defines for clock controls scattered around OMAP chip */ |
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#define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
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#define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
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#define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ |
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#define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ |
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#define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ |
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#define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 |
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#define COM_CLK_DIV_CTRL_SEL 0xfffe0878 |
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#define SOFT_REQ_REG 0xfffe0834 |
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#define SOFT_REQ_REG2 0xfffe0880 |
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extern __u32 arm_idlect1_mask; |
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extern struct clk *api_ck_p, *ck_dpll1_p, *ck_ref_p; |
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extern const struct clkops clkops_dspck; |
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extern const struct clkops clkops_dummy; |
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extern const struct clkops clkops_uart_16xx; |
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extern const struct clkops clkops_generic; |
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/* used for passing SoC type to omap1_{select,round_to}_table_rate() */ |
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extern u32 cpu_mask; |
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#endif
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