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48 lines
1.4 KiB
48 lines
1.4 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Common address map definitions |
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*/ |
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#ifndef __ASM_MACH_ADDR_MAP_H |
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#define __ASM_MACH_ADDR_MAP_H |
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/* APB - Application Subsystem Peripheral Bus |
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* |
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* NOTE: the DMA controller registers are actually on the AXI fabric #1 |
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* slave port to AHB/APB bridge, due to its close relationship to those |
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* peripherals on APB, let's count it into the ABP mapping area. |
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*/ |
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#define APB_PHYS_BASE 0xd4000000 |
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#define APB_VIRT_BASE IOMEM(0xfe000000) |
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#define APB_PHYS_SIZE 0x00200000 |
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#define AXI_PHYS_BASE 0xd4200000 |
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#define AXI_VIRT_BASE IOMEM(0xfe200000) |
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#define AXI_PHYS_SIZE 0x00200000 |
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#define PGU_PHYS_BASE 0xe0000000 |
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#define PGU_VIRT_BASE IOMEM(0xfe400000) |
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#define PGU_PHYS_SIZE 0x00100000 |
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/* Static Memory Controller - Chip Select 0 and 1 */ |
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#define SMC_CS0_PHYS_BASE 0x80000000 |
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#define SMC_CS0_PHYS_SIZE 0x10000000 |
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#define SMC_CS1_PHYS_BASE 0x90000000 |
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#define SMC_CS1_PHYS_SIZE 0x10000000 |
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#define APMU_VIRT_BASE (AXI_VIRT_BASE + 0x82800) |
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#define APMU_REG(x) (APMU_VIRT_BASE + (x)) |
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#define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) |
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#define APBC_REG(x) (APBC_VIRT_BASE + (x)) |
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#define MPMU_VIRT_BASE (APB_VIRT_BASE + 0x50000) |
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#define MPMU_REG(x) (MPMU_VIRT_BASE + (x)) |
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#define CIU_VIRT_BASE (AXI_VIRT_BASE + 0x82c00) |
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#define CIU_REG(x) (CIU_VIRT_BASE + (x)) |
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#define SCU_VIRT_BASE (PGU_VIRT_BASE) |
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#define SCU_REG(x) (SCU_VIRT_BASE + (x)) |
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#endif /* __ASM_MACH_ADDR_MAP_H */
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