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346 lines
8.4 KiB
346 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2013-2014 Linaro Ltd. |
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* Copyright (c) 2013-2014 Hisilicon Limited. |
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*/ |
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#include <linux/init.h> |
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#include <linux/smp.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/memblock.h> |
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#include <linux/of_address.h> |
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#include <asm/cputype.h> |
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#include <asm/cp15.h> |
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#include <asm/cacheflush.h> |
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#include <asm/smp.h> |
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#include <asm/smp_plat.h> |
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#include "core.h" |
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/* bits definition in SC_CPU_RESET_REQ[x]/SC_CPU_RESET_DREQ[x] |
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* 1 -- unreset; 0 -- reset |
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*/ |
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#define CORE_RESET_BIT(x) (1 << x) |
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#define NEON_RESET_BIT(x) (1 << (x + 4)) |
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#define CORE_DEBUG_RESET_BIT(x) (1 << (x + 9)) |
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#define CLUSTER_L2_RESET_BIT (1 << 8) |
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#define CLUSTER_DEBUG_RESET_BIT (1 << 13) |
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/* |
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* bits definition in SC_CPU_RESET_STATUS[x] |
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* 1 -- reset status; 0 -- unreset status |
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*/ |
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#define CORE_RESET_STATUS(x) (1 << x) |
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#define NEON_RESET_STATUS(x) (1 << (x + 4)) |
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#define CORE_DEBUG_RESET_STATUS(x) (1 << (x + 9)) |
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#define CLUSTER_L2_RESET_STATUS (1 << 8) |
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#define CLUSTER_DEBUG_RESET_STATUS (1 << 13) |
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#define CORE_WFI_STATUS(x) (1 << (x + 16)) |
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#define CORE_WFE_STATUS(x) (1 << (x + 20)) |
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#define CORE_DEBUG_ACK(x) (1 << (x + 24)) |
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#define SC_CPU_RESET_REQ(x) (0x520 + (x << 3)) /* reset */ |
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#define SC_CPU_RESET_DREQ(x) (0x524 + (x << 3)) /* unreset */ |
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#define SC_CPU_RESET_STATUS(x) (0x1520 + (x << 3)) |
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#define FAB_SF_MODE 0x0c |
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#define FAB_SF_INVLD 0x10 |
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/* bits definition in FB_SF_INVLD */ |
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#define FB_SF_INVLD_START (1 << 8) |
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#define HIP04_MAX_CLUSTERS 4 |
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#define HIP04_MAX_CPUS_PER_CLUSTER 4 |
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#define POLL_MSEC 10 |
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#define TIMEOUT_MSEC 1000 |
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static void __iomem *sysctrl, *fabric; |
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static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER]; |
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static DEFINE_SPINLOCK(boot_lock); |
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static u32 fabric_phys_addr; |
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/* |
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* [0]: bootwrapper physical address |
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* [1]: bootwrapper size |
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* [2]: relocation address |
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* [3]: relocation size |
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*/ |
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static u32 hip04_boot_method[4]; |
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static bool hip04_cluster_is_down(unsigned int cluster) |
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{ |
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int i; |
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for (i = 0; i < HIP04_MAX_CPUS_PER_CLUSTER; i++) |
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if (hip04_cpu_table[cluster][i]) |
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return false; |
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return true; |
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} |
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static void hip04_set_snoop_filter(unsigned int cluster, unsigned int on) |
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{ |
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unsigned long data; |
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if (!fabric) |
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BUG(); |
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data = readl_relaxed(fabric + FAB_SF_MODE); |
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if (on) |
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data |= 1 << cluster; |
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else |
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data &= ~(1 << cluster); |
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writel_relaxed(data, fabric + FAB_SF_MODE); |
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do { |
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cpu_relax(); |
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} while (data != readl_relaxed(fabric + FAB_SF_MODE)); |
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} |
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static int hip04_boot_secondary(unsigned int l_cpu, struct task_struct *idle) |
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{ |
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unsigned int mpidr, cpu, cluster; |
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unsigned long data; |
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void __iomem *sys_dreq, *sys_status; |
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mpidr = cpu_logical_map(l_cpu); |
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
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if (!sysctrl) |
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return -ENODEV; |
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if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER) |
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return -EINVAL; |
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spin_lock_irq(&boot_lock); |
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if (hip04_cpu_table[cluster][cpu]) |
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goto out; |
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sys_dreq = sysctrl + SC_CPU_RESET_DREQ(cluster); |
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sys_status = sysctrl + SC_CPU_RESET_STATUS(cluster); |
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if (hip04_cluster_is_down(cluster)) { |
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data = CLUSTER_DEBUG_RESET_BIT; |
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writel_relaxed(data, sys_dreq); |
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do { |
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cpu_relax(); |
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data = readl_relaxed(sys_status); |
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} while (data & CLUSTER_DEBUG_RESET_STATUS); |
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hip04_set_snoop_filter(cluster, 1); |
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} |
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data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \ |
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CORE_DEBUG_RESET_BIT(cpu); |
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writel_relaxed(data, sys_dreq); |
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do { |
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cpu_relax(); |
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} while (data == readl_relaxed(sys_status)); |
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/* |
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* We may fail to power up core again without this delay. |
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* It's not mentioned in document. It's found by test. |
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*/ |
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udelay(20); |
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arch_send_wakeup_ipi_mask(cpumask_of(l_cpu)); |
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out: |
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hip04_cpu_table[cluster][cpu]++; |
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spin_unlock_irq(&boot_lock); |
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return 0; |
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} |
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#ifdef CONFIG_HOTPLUG_CPU |
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static void hip04_cpu_die(unsigned int l_cpu) |
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{ |
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unsigned int mpidr, cpu, cluster; |
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bool last_man; |
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mpidr = cpu_logical_map(l_cpu); |
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
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spin_lock(&boot_lock); |
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hip04_cpu_table[cluster][cpu]--; |
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if (hip04_cpu_table[cluster][cpu] == 1) { |
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/* A power_up request went ahead of us. */ |
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spin_unlock(&boot_lock); |
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return; |
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} else if (hip04_cpu_table[cluster][cpu] > 1) { |
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pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu); |
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BUG(); |
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} |
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last_man = hip04_cluster_is_down(cluster); |
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spin_unlock(&boot_lock); |
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if (last_man) { |
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/* Since it's Cortex A15, disable L2 prefetching. */ |
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asm volatile( |
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"mcr p15, 1, %0, c15, c0, 3 \n\t" |
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"isb \n\t" |
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"dsb " |
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: : "r" (0x400) ); |
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v7_exit_coherency_flush(all); |
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} else { |
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v7_exit_coherency_flush(louis); |
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} |
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for (;;) |
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wfi(); |
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} |
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static int hip04_cpu_kill(unsigned int l_cpu) |
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{ |
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unsigned int mpidr, cpu, cluster; |
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unsigned int data, tries, count; |
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mpidr = cpu_logical_map(l_cpu); |
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
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BUG_ON(cluster >= HIP04_MAX_CLUSTERS || |
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cpu >= HIP04_MAX_CPUS_PER_CLUSTER); |
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count = TIMEOUT_MSEC / POLL_MSEC; |
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spin_lock_irq(&boot_lock); |
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for (tries = 0; tries < count; tries++) { |
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if (hip04_cpu_table[cluster][cpu]) |
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goto err; |
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cpu_relax(); |
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data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); |
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if (data & CORE_WFI_STATUS(cpu)) |
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break; |
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spin_unlock_irq(&boot_lock); |
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/* Wait for clean L2 when the whole cluster is down. */ |
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msleep(POLL_MSEC); |
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spin_lock_irq(&boot_lock); |
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} |
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if (tries >= count) |
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goto err; |
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data = CORE_RESET_BIT(cpu) | NEON_RESET_BIT(cpu) | \ |
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CORE_DEBUG_RESET_BIT(cpu); |
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writel_relaxed(data, sysctrl + SC_CPU_RESET_REQ(cluster)); |
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for (tries = 0; tries < count; tries++) { |
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cpu_relax(); |
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data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster)); |
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if (data & CORE_RESET_STATUS(cpu)) |
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break; |
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} |
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if (tries >= count) |
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goto err; |
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if (hip04_cluster_is_down(cluster)) |
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hip04_set_snoop_filter(cluster, 0); |
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spin_unlock_irq(&boot_lock); |
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return 1; |
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err: |
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spin_unlock_irq(&boot_lock); |
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return 0; |
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} |
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#endif |
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static const struct smp_operations hip04_smp_ops __initconst = { |
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.smp_boot_secondary = hip04_boot_secondary, |
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#ifdef CONFIG_HOTPLUG_CPU |
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.cpu_die = hip04_cpu_die, |
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.cpu_kill = hip04_cpu_kill, |
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#endif |
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}; |
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static bool __init hip04_cpu_table_init(void) |
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{ |
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unsigned int mpidr, cpu, cluster; |
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mpidr = read_cpuid_mpidr(); |
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cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0); |
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cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1); |
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if (cluster >= HIP04_MAX_CLUSTERS || |
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cpu >= HIP04_MAX_CPUS_PER_CLUSTER) { |
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pr_err("%s: boot CPU is out of bound!\n", __func__); |
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return false; |
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} |
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hip04_set_snoop_filter(cluster, 1); |
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hip04_cpu_table[cluster][cpu] = 1; |
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return true; |
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} |
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static int __init hip04_smp_init(void) |
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{ |
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struct device_node *np, *np_sctl, *np_fab; |
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struct resource fab_res; |
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void __iomem *relocation; |
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int ret = -ENODEV; |
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np = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-bootwrapper"); |
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if (!np) |
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goto err; |
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ret = of_property_read_u32_array(np, "boot-method", |
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&hip04_boot_method[0], 4); |
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if (ret) |
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goto err; |
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ret = -ENODEV; |
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np_sctl = of_find_compatible_node(NULL, NULL, "hisilicon,sysctrl"); |
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if (!np_sctl) |
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goto err; |
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np_fab = of_find_compatible_node(NULL, NULL, "hisilicon,hip04-fabric"); |
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if (!np_fab) |
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goto err; |
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ret = memblock_reserve(hip04_boot_method[0], hip04_boot_method[1]); |
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if (ret) |
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goto err; |
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relocation = ioremap(hip04_boot_method[2], hip04_boot_method[3]); |
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if (!relocation) { |
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pr_err("failed to map relocation space\n"); |
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ret = -ENOMEM; |
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goto err_reloc; |
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} |
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sysctrl = of_iomap(np_sctl, 0); |
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if (!sysctrl) { |
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pr_err("failed to get sysctrl base\n"); |
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ret = -ENOMEM; |
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goto err_sysctrl; |
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} |
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ret = of_address_to_resource(np_fab, 0, &fab_res); |
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if (ret) { |
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pr_err("failed to get fabric base phys\n"); |
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goto err_fabric; |
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} |
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fabric_phys_addr = fab_res.start; |
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sync_cache_w(&fabric_phys_addr); |
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fabric = of_iomap(np_fab, 0); |
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if (!fabric) { |
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pr_err("failed to get fabric base\n"); |
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ret = -ENOMEM; |
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goto err_fabric; |
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} |
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if (!hip04_cpu_table_init()) { |
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ret = -EINVAL; |
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goto err_table; |
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} |
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/* |
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* Fill the instruction address that is used after secondary core |
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* out of reset. |
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*/ |
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writel_relaxed(hip04_boot_method[0], relocation); |
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writel_relaxed(0xa5a5a5a5, relocation + 4); /* magic number */ |
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writel_relaxed(__pa_symbol(secondary_startup), relocation + 8); |
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writel_relaxed(0, relocation + 12); |
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iounmap(relocation); |
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smp_set_ops(&hip04_smp_ops); |
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return ret; |
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err_table: |
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iounmap(fabric); |
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err_fabric: |
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iounmap(sysctrl); |
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err_sysctrl: |
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iounmap(relocation); |
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err_reloc: |
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memblock_free(hip04_boot_method[0], hip04_boot_method[1]); |
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err: |
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return ret; |
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} |
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early_initcall(hip04_smp_init);
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