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136 lines
3.2 KiB
136 lines
3.2 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* linux/arch/arm/mach-footbridge/dc21285-timer.c |
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* |
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* Copyright (C) 1998 Russell King. |
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* Copyright (C) 1998 Phil Blundell |
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*/ |
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#include <linux/clockchips.h> |
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#include <linux/clocksource.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irq.h> |
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#include <linux/sched_clock.h> |
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#include <asm/irq.h> |
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#include <asm/hardware/dec21285.h> |
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#include <asm/mach/time.h> |
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#include <asm/system_info.h> |
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#include "common.h" |
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static u64 cksrc_dc21285_read(struct clocksource *cs) |
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{ |
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return cs->mask - *CSR_TIMER2_VALUE; |
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} |
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static int cksrc_dc21285_enable(struct clocksource *cs) |
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{ |
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*CSR_TIMER2_LOAD = cs->mask; |
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*CSR_TIMER2_CLR = 0; |
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*CSR_TIMER2_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; |
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return 0; |
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} |
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static void cksrc_dc21285_disable(struct clocksource *cs) |
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{ |
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*CSR_TIMER2_CNTL = 0; |
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} |
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static struct clocksource cksrc_dc21285 = { |
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.name = "dc21285_timer2", |
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.rating = 200, |
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.read = cksrc_dc21285_read, |
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.enable = cksrc_dc21285_enable, |
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.disable = cksrc_dc21285_disable, |
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.mask = CLOCKSOURCE_MASK(24), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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}; |
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static int ckevt_dc21285_set_next_event(unsigned long delta, |
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struct clock_event_device *c) |
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{ |
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*CSR_TIMER1_CLR = 0; |
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*CSR_TIMER1_LOAD = delta; |
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*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; |
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return 0; |
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} |
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static int ckevt_dc21285_shutdown(struct clock_event_device *c) |
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{ |
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*CSR_TIMER1_CNTL = 0; |
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return 0; |
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} |
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static int ckevt_dc21285_set_periodic(struct clock_event_device *c) |
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{ |
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*CSR_TIMER1_CLR = 0; |
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*CSR_TIMER1_LOAD = (mem_fclk_21285 + 8 * HZ) / (16 * HZ); |
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*CSR_TIMER1_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_AUTORELOAD | |
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TIMER_CNTL_DIV16; |
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return 0; |
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} |
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static struct clock_event_device ckevt_dc21285 = { |
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.name = "dc21285_timer1", |
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.features = CLOCK_EVT_FEAT_PERIODIC | |
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CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 200, |
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.irq = IRQ_TIMER1, |
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.set_next_event = ckevt_dc21285_set_next_event, |
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.set_state_shutdown = ckevt_dc21285_shutdown, |
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.set_state_periodic = ckevt_dc21285_set_periodic, |
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.set_state_oneshot = ckevt_dc21285_shutdown, |
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.tick_resume = ckevt_dc21285_set_periodic, |
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}; |
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static irqreturn_t timer1_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *ce = dev_id; |
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*CSR_TIMER1_CLR = 0; |
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/* Stop the timer if in one-shot mode */ |
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if (clockevent_state_oneshot(ce)) |
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*CSR_TIMER1_CNTL = 0; |
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ce->event_handler(ce); |
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return IRQ_HANDLED; |
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} |
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/* |
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* Set up timer interrupt. |
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*/ |
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void __init footbridge_timer_init(void) |
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{ |
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struct clock_event_device *ce = &ckevt_dc21285; |
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unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); |
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clocksource_register_hz(&cksrc_dc21285, rate); |
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if (request_irq(ce->irq, timer1_interrupt, IRQF_TIMER | IRQF_IRQPOLL, |
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"dc21285_timer1", &ckevt_dc21285)) |
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pr_err("Failed to request irq %d (dc21285_timer1)", ce->irq); |
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ce->cpumask = cpumask_of(smp_processor_id()); |
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clockevents_config_and_register(ce, rate, 0x4, 0xffffff); |
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} |
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static u64 notrace footbridge_read_sched_clock(void) |
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{ |
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return ~*CSR_TIMER3_VALUE; |
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} |
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void __init footbridge_sched_clock(void) |
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{ |
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unsigned rate = DIV_ROUND_CLOSEST(mem_fclk_21285, 16); |
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*CSR_TIMER3_LOAD = 0; |
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*CSR_TIMER3_CLR = 0; |
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*CSR_TIMER3_CNTL = TIMER_CNTL_ENABLE | TIMER_CNTL_DIV16; |
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sched_clock_register(footbridge_read_sched_clock, 24, rate); |
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}
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