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312 lines
8.4 KiB
312 lines
8.4 KiB
// SPDX-License-Identifier: GPL-2.0 |
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// Copyright (c) 2014 Samsung Electronics Co., Ltd. |
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// http://www.samsung.com |
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// |
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// Based on arch/arm/mach-vexpress/dcscb.c |
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#include <linux/arm-cci.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/syscore_ops.h> |
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#include <linux/soc/samsung/exynos-regs-pmu.h> |
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#include <asm/cputype.h> |
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#include <asm/cp15.h> |
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#include <asm/mcpm.h> |
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#include <asm/smp_plat.h> |
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#include "common.h" |
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#define EXYNOS5420_CPUS_PER_CLUSTER 4 |
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#define EXYNOS5420_NR_CLUSTERS 2 |
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#define EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN BIT(9) |
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#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29) |
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#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30) |
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static void __iomem *ns_sram_base_addr __ro_after_init; |
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static bool secure_firmware __ro_after_init; |
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/* |
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* The common v7_exit_coherency_flush API could not be used because of the |
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* Erratum 799270 workaround. This macro is the same as the common one (in |
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* arch/arm/include/asm/cacheflush.h) except for the erratum handling. |
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*/ |
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#define exynos_v7_exit_coherency_flush(level) \ |
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asm volatile( \ |
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"stmfd sp!, {fp, ip}\n\t"\ |
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"mrc p15, 0, r0, c1, c0, 0 @ get SCTLR\n\t" \ |
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"bic r0, r0, #"__stringify(CR_C)"\n\t" \ |
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"mcr p15, 0, r0, c1, c0, 0 @ set SCTLR\n\t" \ |
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"isb\n\t"\ |
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"bl v7_flush_dcache_"__stringify(level)"\n\t" \ |
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"mrc p15, 0, r0, c1, c0, 1 @ get ACTLR\n\t" \ |
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"bic r0, r0, #(1 << 6) @ disable local coherency\n\t" \ |
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/* Dummy Load of a device register to avoid Erratum 799270 */ \ |
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"ldr r4, [%0]\n\t" \ |
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"and r4, r4, #0\n\t" \ |
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"orr r0, r0, r4\n\t" \ |
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"mcr p15, 0, r0, c1, c0, 1 @ set ACTLR\n\t" \ |
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"isb\n\t" \ |
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"dsb\n\t" \ |
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"ldmfd sp!, {fp, ip}" \ |
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: \ |
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: "Ir" (pmu_base_addr + S5P_INFORM0) \ |
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: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ |
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"r9", "r10", "lr", "memory") |
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static int exynos_cpu_powerup(unsigned int cpu, unsigned int cluster) |
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{ |
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); |
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bool state; |
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
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if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER || |
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cluster >= EXYNOS5420_NR_CLUSTERS) |
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return -EINVAL; |
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state = exynos_cpu_power_state(cpunr); |
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exynos_cpu_power_up(cpunr); |
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if (!state && secure_firmware) { |
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/* |
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* This assumes the cluster number of the big cores(Cortex A15) |
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* is 0 and the Little cores(Cortex A7) is 1. |
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* When the system was booted from the Little core, |
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* they should be reset during power up cpu. |
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*/ |
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if (cluster && |
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cluster == MPIDR_AFFINITY_LEVEL(cpu_logical_map(0), 1)) { |
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unsigned int timeout = 16; |
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/* |
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* Before we reset the Little cores, we should wait |
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* the SPARE2 register is set to 1 because the init |
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* codes of the iROM will set the register after |
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* initialization. |
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*/ |
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while (timeout && !pmu_raw_readl(S5P_PMU_SPARE2)) { |
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timeout--; |
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udelay(10); |
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} |
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if (timeout == 0) { |
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pr_err("cpu %u cluster %u powerup failed\n", |
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cpu, cluster); |
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exynos_cpu_power_down(cpunr); |
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return -ETIMEDOUT; |
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} |
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pmu_raw_writel(EXYNOS5420_KFC_CORE_RESET(cpu), |
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EXYNOS_SWRESET); |
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} |
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} |
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return 0; |
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} |
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static int exynos_cluster_powerup(unsigned int cluster) |
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{ |
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pr_debug("%s: cluster %u\n", __func__, cluster); |
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if (cluster >= EXYNOS5420_NR_CLUSTERS) |
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return -EINVAL; |
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exynos_cluster_power_up(cluster); |
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return 0; |
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} |
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static void exynos_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) |
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{ |
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); |
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || |
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cluster >= EXYNOS5420_NR_CLUSTERS); |
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exynos_cpu_power_down(cpunr); |
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} |
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static void exynos_cluster_powerdown_prepare(unsigned int cluster) |
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{ |
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pr_debug("%s: cluster %u\n", __func__, cluster); |
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BUG_ON(cluster >= EXYNOS5420_NR_CLUSTERS); |
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exynos_cluster_power_down(cluster); |
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} |
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static void exynos_cpu_cache_disable(void) |
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{ |
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/* Disable and flush the local CPU cache. */ |
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exynos_v7_exit_coherency_flush(louis); |
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} |
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static void exynos_cluster_cache_disable(void) |
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{ |
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A15) { |
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/* |
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* On the Cortex-A15 we need to disable |
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* L2 prefetching before flushing the cache. |
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*/ |
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asm volatile( |
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"mcr p15, 1, %0, c15, c0, 3\n\t" |
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"isb\n\t" |
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"dsb" |
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: : "r" (0x400)); |
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} |
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/* Flush all cache levels for this cluster. */ |
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exynos_v7_exit_coherency_flush(all); |
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/* |
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* Disable cluster-level coherency by masking |
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* incoming snoops and DVM messages: |
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*/ |
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cci_disable_port_by_cpu(read_cpuid_mpidr()); |
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} |
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static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster) |
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{ |
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unsigned int tries = 100; |
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unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER); |
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pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); |
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BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER || |
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cluster >= EXYNOS5420_NR_CLUSTERS); |
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/* Wait for the core state to be OFF */ |
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while (tries--) { |
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if ((exynos_cpu_power_state(cpunr) == 0)) |
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return 0; /* success: the CPU is halted */ |
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/* Otherwise, wait and retry: */ |
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msleep(1); |
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} |
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return -ETIMEDOUT; /* timeout */ |
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} |
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static void exynos_cpu_is_up(unsigned int cpu, unsigned int cluster) |
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{ |
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/* especially when resuming: make sure power control is set */ |
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exynos_cpu_powerup(cpu, cluster); |
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} |
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static const struct mcpm_platform_ops exynos_power_ops = { |
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.cpu_powerup = exynos_cpu_powerup, |
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.cluster_powerup = exynos_cluster_powerup, |
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.cpu_powerdown_prepare = exynos_cpu_powerdown_prepare, |
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.cluster_powerdown_prepare = exynos_cluster_powerdown_prepare, |
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.cpu_cache_disable = exynos_cpu_cache_disable, |
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.cluster_cache_disable = exynos_cluster_cache_disable, |
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.wait_for_powerdown = exynos_wait_for_powerdown, |
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.cpu_is_up = exynos_cpu_is_up, |
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}; |
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/* |
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* Enable cluster-level coherency, in preparation for turning on the MMU. |
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*/ |
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static void __naked exynos_pm_power_up_setup(unsigned int affinity_level) |
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{ |
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asm volatile ("\n" |
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"cmp r0, #1\n" |
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"bxne lr\n" |
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"b cci_enable_port_for_self"); |
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} |
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static const struct of_device_id exynos_dt_mcpm_match[] = { |
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{ .compatible = "samsung,exynos5420" }, |
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{ .compatible = "samsung,exynos5800" }, |
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{}, |
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}; |
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static void exynos_mcpm_setup_entry_point(void) |
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{ |
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/* |
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* U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr |
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* as part of secondary_cpu_start(). Let's redirect it to the |
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* mcpm_entry_point(). This is done during both secondary boot-up as |
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* well as system resume. |
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*/ |
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__raw_writel(0xe59f0000, ns_sram_base_addr); /* ldr r0, [pc, #0] */ |
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__raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx r0 */ |
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__raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8); |
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} |
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static struct syscore_ops exynos_mcpm_syscore_ops = { |
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.resume = exynos_mcpm_setup_entry_point, |
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}; |
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static int __init exynos_mcpm_init(void) |
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{ |
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struct device_node *node; |
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unsigned int value, i; |
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int ret; |
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node = of_find_matching_node(NULL, exynos_dt_mcpm_match); |
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if (!node) |
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return -ENODEV; |
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of_node_put(node); |
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if (!cci_probed()) |
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return -ENODEV; |
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node = of_find_compatible_node(NULL, NULL, |
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"samsung,exynos4210-sysram-ns"); |
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if (!node) |
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return -ENODEV; |
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ns_sram_base_addr = of_iomap(node, 0); |
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of_node_put(node); |
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if (!ns_sram_base_addr) { |
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pr_err("failed to map non-secure iRAM base address\n"); |
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return -ENOMEM; |
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} |
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secure_firmware = exynos_secure_firmware_available(); |
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/* |
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* To increase the stability of KFC reset we need to program |
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* the PMU SPARE3 register |
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*/ |
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pmu_raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3); |
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ret = mcpm_platform_register(&exynos_power_ops); |
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if (!ret) |
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ret = mcpm_sync_init(exynos_pm_power_up_setup); |
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if (!ret) |
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ret = mcpm_loopback(exynos_cluster_cache_disable); /* turn on the CCI */ |
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if (ret) { |
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iounmap(ns_sram_base_addr); |
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return ret; |
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} |
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mcpm_smp_set_ops(); |
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pr_info("Exynos MCPM support installed\n"); |
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/* |
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* On Exynos5420/5800 for the A15 and A7 clusters: |
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* |
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* EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN ensures that all the cores |
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* in a cluster are turned off before turning off the cluster L2. |
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* |
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* EXYNOS5420_USE_ARM_CORE_DOWN_STATE ensures that a cores is powered |
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* off before waking it up. |
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* |
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* EXYNOS5420_USE_L2_COMMON_UP_STATE ensures that cluster L2 will be |
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* turned on before the first man is powered up. |
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*/ |
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for (i = 0; i < EXYNOS5420_NR_CLUSTERS; i++) { |
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value = pmu_raw_readl(EXYNOS_COMMON_OPTION(i)); |
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value |= EXYNOS5420_ENABLE_AUTOMATIC_CORE_DOWN | |
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EXYNOS5420_USE_ARM_CORE_DOWN_STATE | |
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EXYNOS5420_USE_L2_COMMON_UP_STATE; |
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pmu_raw_writel(value, EXYNOS_COMMON_OPTION(i)); |
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} |
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exynos_mcpm_setup_entry_point(); |
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register_syscore_ops(&exynos_mcpm_syscore_ops); |
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return ret; |
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} |
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early_initcall(exynos_mcpm_init);
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