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223 lines
5.1 KiB
223 lines
5.1 KiB
/* |
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* arch/arm/mach-dove/pcie.c |
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* |
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* PCIe functions for Marvell Dove 88AP510 SoC |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/pci.h> |
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#include <linux/clk.h> |
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#include <video/vga.h> |
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#include <asm/mach/pci.h> |
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#include <asm/mach/arch.h> |
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#include <asm/setup.h> |
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#include <asm/delay.h> |
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#include <plat/pcie.h> |
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#include <plat/addr-map.h> |
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#include "irqs.h" |
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#include "bridge-regs.h" |
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#include "common.h" |
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struct pcie_port { |
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u8 index; |
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u8 root_bus_nr; |
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void __iomem *base; |
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spinlock_t conf_lock; |
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char mem_space_name[16]; |
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struct resource res; |
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}; |
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static struct pcie_port pcie_port[2]; |
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static int num_pcie_ports; |
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static int __init dove_pcie_setup(int nr, struct pci_sys_data *sys) |
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{ |
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struct pcie_port *pp; |
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if (nr >= num_pcie_ports) |
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return 0; |
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pp = &pcie_port[nr]; |
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sys->private_data = pp; |
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pp->root_bus_nr = sys->busnr; |
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/* |
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* Generic PCIe unit setup. |
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*/ |
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orion_pcie_set_local_bus_nr(pp->base, sys->busnr); |
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orion_pcie_setup(pp->base); |
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if (pp->index == 0) |
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pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE); |
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else |
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pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE); |
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/* |
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* IORESOURCE_MEM |
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*/ |
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snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), |
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"PCIe %d MEM", pp->index); |
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pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0; |
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pp->res.name = pp->mem_space_name; |
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if (pp->index == 0) { |
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pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE; |
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pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1; |
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} else { |
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pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE; |
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pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1; |
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} |
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pp->res.flags = IORESOURCE_MEM; |
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if (request_resource(&iomem_resource, &pp->res)) |
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panic("Request PCIe Memory resource failed\n"); |
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pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset); |
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return 1; |
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} |
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static int pcie_valid_config(struct pcie_port *pp, int bus, int dev) |
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{ |
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/* |
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* Don't go out when trying to access nonexisting devices |
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* on the local bus. |
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*/ |
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if (bus == pp->root_bus_nr && dev > 1) |
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return 0; |
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return 1; |
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} |
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static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where, |
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int size, u32 *val) |
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{ |
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struct pci_sys_data *sys = bus->sysdata; |
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struct pcie_port *pp = sys->private_data; |
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unsigned long flags; |
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int ret; |
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) { |
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*val = 0xffffffff; |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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} |
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spin_lock_irqsave(&pp->conf_lock, flags); |
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ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val); |
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spin_unlock_irqrestore(&pp->conf_lock, flags); |
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return ret; |
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} |
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static int pcie_wr_conf(struct pci_bus *bus, u32 devfn, |
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int where, int size, u32 val) |
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{ |
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struct pci_sys_data *sys = bus->sysdata; |
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struct pcie_port *pp = sys->private_data; |
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unsigned long flags; |
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int ret; |
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if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) |
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return PCIBIOS_DEVICE_NOT_FOUND; |
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spin_lock_irqsave(&pp->conf_lock, flags); |
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ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val); |
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spin_unlock_irqrestore(&pp->conf_lock, flags); |
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return ret; |
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} |
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static struct pci_ops pcie_ops = { |
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.read = pcie_rd_conf, |
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.write = pcie_wr_conf, |
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}; |
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static void rc_pci_fixup(struct pci_dev *dev) |
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{ |
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/* |
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* Prevent enumeration of root complex. |
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*/ |
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if (dev->bus->parent == NULL && dev->devfn == 0) { |
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int i; |
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
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dev->resource[i].start = 0; |
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dev->resource[i].end = 0; |
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dev->resource[i].flags = 0; |
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} |
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} |
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} |
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); |
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static int __init |
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dove_pcie_scan_bus(int nr, struct pci_host_bridge *bridge) |
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{ |
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struct pci_sys_data *sys = pci_host_bridge_priv(bridge); |
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if (nr >= num_pcie_ports) { |
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BUG(); |
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return -EINVAL; |
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} |
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list_splice_init(&sys->resources, &bridge->windows); |
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bridge->dev.parent = NULL; |
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bridge->sysdata = sys; |
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bridge->busnr = sys->busnr; |
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bridge->ops = &pcie_ops; |
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return pci_scan_root_bus_bridge(bridge); |
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} |
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static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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struct pci_sys_data *sys = dev->sysdata; |
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struct pcie_port *pp = sys->private_data; |
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return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0; |
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} |
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static struct hw_pci dove_pci __initdata = { |
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.nr_controllers = 2, |
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.setup = dove_pcie_setup, |
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.scan = dove_pcie_scan_bus, |
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.map_irq = dove_pcie_map_irq, |
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}; |
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static void __init add_pcie_port(int index, void __iomem *base) |
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{ |
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printk(KERN_INFO "Dove PCIe port %d: ", index); |
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if (orion_pcie_link_up(base)) { |
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struct pcie_port *pp = &pcie_port[num_pcie_ports++]; |
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struct clk *clk = clk_get_sys("pcie", (index ? "1" : "0")); |
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if (!IS_ERR(clk)) |
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clk_prepare_enable(clk); |
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printk(KERN_INFO "link up\n"); |
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pp->index = index; |
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pp->root_bus_nr = -1; |
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pp->base = base; |
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spin_lock_init(&pp->conf_lock); |
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memset(&pp->res, 0, sizeof(pp->res)); |
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} else { |
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printk(KERN_INFO "link down, ignoring\n"); |
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} |
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} |
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void __init dove_pcie_init(int init_port0, int init_port1) |
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{ |
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vga_base = DOVE_PCIE0_MEM_PHYS_BASE; |
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if (init_port0) |
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add_pcie_port(0, DOVE_PCIE0_VIRT_BASE); |
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if (init_port1) |
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add_pcie_port(1, DOVE_PCIE1_VIRT_BASE); |
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pci_common_init(&dove_pci); |
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}
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