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171 lines
4.1 KiB
171 lines
4.1 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* DaVinci Power Management Routines |
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* |
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* Copyright (C) 2009 Texas Instruments, Inc. https://www.ti.com/ |
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*/ |
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#include <linux/pm.h> |
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#include <linux/suspend.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/spinlock.h> |
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#include <asm/cacheflush.h> |
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#include <asm/delay.h> |
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#include <asm/io.h> |
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#include <mach/common.h> |
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#include <mach/da8xx.h> |
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#include <mach/mux.h> |
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#include <mach/pm.h> |
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#include "clock.h" |
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#include "psc.h" |
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#include "sram.h" |
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#define DA850_PLL1_BASE 0x01e1a000 |
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#define DEEPSLEEP_SLEEPCOUNT_MASK 0xFFFF |
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#define DEEPSLEEP_SLEEPCOUNT 128 |
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static void (*davinci_sram_suspend) (struct davinci_pm_config *); |
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static struct davinci_pm_config pm_config = { |
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.sleepcount = DEEPSLEEP_SLEEPCOUNT, |
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.ddrpsc_num = DA8XX_LPSC1_EMIF3C, |
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}; |
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static void davinci_sram_push(void *dest, void *src, unsigned int size) |
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{ |
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memcpy(dest, src, size); |
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flush_icache_range((unsigned long)dest, (unsigned long)(dest + size)); |
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} |
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static void davinci_pm_suspend(void) |
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{ |
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unsigned val; |
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if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { |
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/* Switch CPU PLL to bypass mode */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN); |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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udelay(PLL_BYPASS_TIME); |
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/* Powerdown CPU PLL */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val |= PLLCTL_PLLPWRDN; |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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} |
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/* Configure sleep count in deep sleep register */ |
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val = __raw_readl(pm_config.deepsleep_reg); |
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val &= ~DEEPSLEEP_SLEEPCOUNT_MASK, |
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val |= pm_config.sleepcount; |
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__raw_writel(val, pm_config.deepsleep_reg); |
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/* System goes to sleep in this call */ |
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davinci_sram_suspend(&pm_config); |
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if (pm_config.cpupll_reg_base != pm_config.ddrpll_reg_base) { |
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/* put CPU PLL in reset */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val &= ~PLLCTL_PLLRST; |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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/* put CPU PLL in power down */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val &= ~PLLCTL_PLLPWRDN; |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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/* wait for CPU PLL reset */ |
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udelay(PLL_RESET_TIME); |
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/* bring CPU PLL out of reset */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val |= PLLCTL_PLLRST; |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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/* Wait for CPU PLL to lock */ |
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udelay(PLL_LOCK_TIME); |
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/* Remove CPU PLL from bypass mode */ |
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val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); |
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val &= ~PLLCTL_PLLENSRC; |
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val |= PLLCTL_PLLEN; |
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__raw_writel(val, pm_config.cpupll_reg_base + PLLCTL); |
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} |
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} |
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static int davinci_pm_enter(suspend_state_t state) |
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{ |
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int ret = 0; |
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switch (state) { |
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case PM_SUSPEND_MEM: |
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davinci_pm_suspend(); |
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break; |
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default: |
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ret = -EINVAL; |
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} |
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return ret; |
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} |
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static const struct platform_suspend_ops davinci_pm_ops = { |
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.enter = davinci_pm_enter, |
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.valid = suspend_valid_only_mem, |
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}; |
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int __init davinci_pm_init(void) |
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{ |
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int ret; |
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ret = davinci_cfg_reg(DA850_RTC_ALARM); |
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if (ret) |
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return ret; |
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pm_config.ddr2_ctlr_base = da8xx_get_mem_ctlr(); |
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pm_config.deepsleep_reg = DA8XX_SYSCFG1_VIRT(DA8XX_DEEPSLEEP_REG); |
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pm_config.cpupll_reg_base = ioremap(DA8XX_PLL0_BASE, SZ_4K); |
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if (!pm_config.cpupll_reg_base) |
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return -ENOMEM; |
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pm_config.ddrpll_reg_base = ioremap(DA850_PLL1_BASE, SZ_4K); |
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if (!pm_config.ddrpll_reg_base) { |
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ret = -ENOMEM; |
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goto no_ddrpll_mem; |
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} |
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pm_config.ddrpsc_reg_base = ioremap(DA8XX_PSC1_BASE, SZ_4K); |
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if (!pm_config.ddrpsc_reg_base) { |
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ret = -ENOMEM; |
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goto no_ddrpsc_mem; |
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} |
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davinci_sram_suspend = sram_alloc(davinci_cpu_suspend_sz, NULL); |
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if (!davinci_sram_suspend) { |
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pr_err("PM: cannot allocate SRAM memory\n"); |
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ret = -ENOMEM; |
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goto no_sram_mem; |
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} |
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davinci_sram_push(davinci_sram_suspend, davinci_cpu_suspend, |
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davinci_cpu_suspend_sz); |
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suspend_set_ops(&davinci_pm_ops); |
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return 0; |
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no_sram_mem: |
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iounmap(pm_config.ddrpsc_reg_base); |
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no_ddrpsc_mem: |
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iounmap(pm_config.ddrpll_reg_base); |
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no_ddrpll_mem: |
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iounmap(pm_config.cpupll_reg_base); |
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return ret; |
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}
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