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635 lines
14 KiB
635 lines
14 KiB
/* |
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* Critical Link MityOMAP-L138 SoM |
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* |
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* Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com |
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* |
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* This file is licensed under the terms of the GNU General Public License |
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* version 2. This program is licensed "as is" without any warranty of |
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* any kind, whether express or implied. |
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*/ |
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|
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#define pr_fmt(fmt) "MityOMAPL138: " fmt |
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|
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/console.h> |
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#include <linux/platform_device.h> |
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#include <linux/property.h> |
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#include <linux/mtd/partitions.h> |
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#include <linux/notifier.h> |
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#include <linux/nvmem-consumer.h> |
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#include <linux/nvmem-provider.h> |
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#include <linux/regulator/machine.h> |
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#include <linux/i2c.h> |
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#include <linux/etherdevice.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/flash.h> |
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|
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#include <asm/io.h> |
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#include <asm/mach-types.h> |
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#include <asm/mach/arch.h> |
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#include <mach/common.h> |
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#include <mach/da8xx.h> |
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#include <linux/platform_data/mtd-davinci.h> |
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#include <linux/platform_data/mtd-davinci-aemif.h> |
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#include <linux/platform_data/ti-aemif.h> |
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#include <mach/mux.h> |
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#include <linux/platform_data/spi-davinci.h> |
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|
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#define MITYOMAPL138_PHY_ID "" |
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|
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#define FACTORY_CONFIG_MAGIC 0x012C0138 |
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#define FACTORY_CONFIG_VERSION 0x00010001 |
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|
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/* Data Held in On-Board I2C device */ |
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struct factory_config { |
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u32 magic; |
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u32 version; |
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u8 mac[6]; |
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u32 fpga_type; |
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u32 spare; |
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u32 serialnumber; |
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char partnum[32]; |
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}; |
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static struct factory_config factory_config; |
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|
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#ifdef CONFIG_CPU_FREQ |
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struct part_no_info { |
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const char *part_no; /* part number string of interest */ |
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int max_freq; /* khz */ |
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}; |
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static struct part_no_info mityomapl138_pn_info[] = { |
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{ |
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.part_no = "L138-C", |
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.max_freq = 300000, |
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}, |
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{ |
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.part_no = "L138-D", |
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.max_freq = 375000, |
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}, |
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{ |
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.part_no = "L138-F", |
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.max_freq = 456000, |
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}, |
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{ |
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.part_no = "1808-C", |
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.max_freq = 300000, |
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}, |
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{ |
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.part_no = "1808-D", |
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.max_freq = 375000, |
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}, |
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{ |
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.part_no = "1808-F", |
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.max_freq = 456000, |
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}, |
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{ |
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.part_no = "1810-D", |
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.max_freq = 375000, |
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}, |
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}; |
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static void mityomapl138_cpufreq_init(const char *partnum) |
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{ |
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int i, ret; |
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for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) { |
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/* |
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* the part number has additional characters beyond what is |
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* stored in the table. This information is not needed for |
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* determining the speed grade, and would require several |
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* more table entries. Only check the first N characters |
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* for a match. |
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*/ |
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if (!strncmp(partnum, mityomapl138_pn_info[i].part_no, |
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strlen(mityomapl138_pn_info[i].part_no))) { |
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da850_max_speed = mityomapl138_pn_info[i].max_freq; |
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break; |
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} |
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} |
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ret = da850_register_cpufreq("pll0_sysclk3"); |
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if (ret) |
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pr_warn("cpufreq registration failed: %d\n", ret); |
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} |
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#else |
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static void mityomapl138_cpufreq_init(const char *partnum) { } |
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#endif |
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static int read_factory_config(struct notifier_block *nb, |
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unsigned long event, void *data) |
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{ |
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int ret; |
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const char *partnum = NULL; |
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struct nvmem_device *nvmem = data; |
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if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0) |
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return NOTIFY_DONE; |
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if (!IS_BUILTIN(CONFIG_NVMEM)) { |
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pr_warn("Factory Config not available without CONFIG_NVMEM\n"); |
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goto bad_config; |
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} |
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ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), |
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&factory_config); |
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if (ret != sizeof(struct factory_config)) { |
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pr_warn("Read Factory Config Failed: %d\n", ret); |
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goto bad_config; |
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} |
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if (factory_config.magic != FACTORY_CONFIG_MAGIC) { |
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pr_warn("Factory Config Magic Wrong (%X)\n", |
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factory_config.magic); |
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goto bad_config; |
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} |
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if (factory_config.version != FACTORY_CONFIG_VERSION) { |
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pr_warn("Factory Config Version Wrong (%X)\n", |
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factory_config.version); |
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goto bad_config; |
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} |
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partnum = factory_config.partnum; |
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pr_info("Part Number = %s\n", partnum); |
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bad_config: |
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/* default maximum speed is valid for all platforms */ |
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mityomapl138_cpufreq_init(partnum); |
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return NOTIFY_STOP; |
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} |
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static struct notifier_block mityomapl138_nvmem_notifier = { |
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.notifier_call = read_factory_config, |
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}; |
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/* |
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* We don't define a cell for factory config as it will be accessed from the |
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* board file using the nvmem notifier chain. |
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*/ |
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static struct nvmem_cell_info mityomapl138_nvmem_cells[] = { |
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{ |
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.name = "macaddr", |
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.offset = 0x64, |
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.bytes = ETH_ALEN, |
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} |
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}; |
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static struct nvmem_cell_table mityomapl138_nvmem_cell_table = { |
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.nvmem_name = "1-00500", |
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.cells = mityomapl138_nvmem_cells, |
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.ncells = ARRAY_SIZE(mityomapl138_nvmem_cells), |
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}; |
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static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = { |
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.nvmem_name = "1-00500", |
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.cell_name = "macaddr", |
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.dev_id = "davinci_emac.1", |
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.con_id = "mac-address", |
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}; |
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static const struct property_entry mityomapl138_fd_chip_properties[] = { |
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PROPERTY_ENTRY_U32("pagesize", 8), |
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PROPERTY_ENTRY_BOOL("read-only"), |
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{ } |
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}; |
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static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { |
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.bus_freq = 100, /* kHz */ |
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.bus_delay = 0, /* usec */ |
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}; |
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/* TPS65023 voltage regulator support */ |
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/* 1.2V Core */ |
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static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { |
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{ |
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.supply = "cvdd", |
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}, |
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}; |
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/* 1.8V */ |
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static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { |
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{ |
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.supply = "usb0_vdda18", |
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}, |
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{ |
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.supply = "usb1_vdda18", |
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}, |
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{ |
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.supply = "ddr_dvdd18", |
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}, |
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{ |
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.supply = "sata_vddr", |
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}, |
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}; |
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/* 1.2V */ |
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static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { |
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{ |
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.supply = "sata_vdd", |
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}, |
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{ |
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.supply = "usb_cvdd", |
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}, |
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{ |
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.supply = "pll0_vdda", |
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}, |
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{ |
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.supply = "pll1_vdda", |
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}, |
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}; |
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/* 1.8V Aux LDO, not used */ |
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static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { |
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{ |
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.supply = "1.8v_aux", |
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}, |
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}; |
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/* FPGA VCC Aux (2.5 or 3.3) LDO */ |
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static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { |
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{ |
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.supply = "vccaux", |
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}, |
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}; |
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static struct regulator_init_data tps65023_regulator_data[] = { |
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/* dcdc1 */ |
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{ |
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.constraints = { |
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.min_uV = 1150000, |
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.max_uV = 1350000, |
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
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REGULATOR_CHANGE_STATUS, |
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.boot_on = 1, |
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}, |
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), |
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.consumer_supplies = tps65023_dcdc1_consumers, |
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}, |
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/* dcdc2 */ |
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{ |
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.constraints = { |
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.min_uV = 1800000, |
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.max_uV = 1800000, |
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.valid_ops_mask = REGULATOR_CHANGE_STATUS, |
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.boot_on = 1, |
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}, |
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), |
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.consumer_supplies = tps65023_dcdc2_consumers, |
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}, |
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/* dcdc3 */ |
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{ |
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.constraints = { |
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.min_uV = 1200000, |
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.max_uV = 1200000, |
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.valid_ops_mask = REGULATOR_CHANGE_STATUS, |
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.boot_on = 1, |
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}, |
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.num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), |
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.consumer_supplies = tps65023_dcdc3_consumers, |
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}, |
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/* ldo1 */ |
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{ |
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.constraints = { |
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.min_uV = 1800000, |
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.max_uV = 1800000, |
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.valid_ops_mask = REGULATOR_CHANGE_STATUS, |
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.boot_on = 1, |
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}, |
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.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), |
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.consumer_supplies = tps65023_ldo1_consumers, |
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}, |
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/* ldo2 */ |
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{ |
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.constraints = { |
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.min_uV = 2500000, |
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.max_uV = 3300000, |
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.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
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REGULATOR_CHANGE_STATUS, |
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.boot_on = 1, |
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}, |
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.num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), |
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.consumer_supplies = tps65023_ldo2_consumers, |
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}, |
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}; |
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static struct i2c_board_info __initdata mityomap_tps65023_info[] = { |
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{ |
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I2C_BOARD_INFO("tps65023", 0x48), |
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.platform_data = &tps65023_regulator_data[0], |
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}, |
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{ |
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I2C_BOARD_INFO("24c02", 0x50), |
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.properties = mityomapl138_fd_chip_properties, |
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}, |
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}; |
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static int __init pmic_tps65023_init(void) |
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{ |
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return i2c_register_board_info(1, mityomap_tps65023_info, |
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ARRAY_SIZE(mityomap_tps65023_info)); |
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} |
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/* |
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* SPI Devices: |
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* SPI1_CS0: 8M Flash ST-M25P64-VME6G |
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*/ |
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static struct mtd_partition spi_flash_partitions[] = { |
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[0] = { |
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.name = "ubl", |
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.offset = 0, |
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.size = SZ_64K, |
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.mask_flags = MTD_WRITEABLE, |
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}, |
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[1] = { |
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.name = "u-boot", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_512K, |
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.mask_flags = MTD_WRITEABLE, |
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}, |
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[2] = { |
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.name = "u-boot-env", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_64K, |
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.mask_flags = MTD_WRITEABLE, |
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}, |
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[3] = { |
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.name = "periph-config", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_64K, |
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.mask_flags = MTD_WRITEABLE, |
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}, |
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[4] = { |
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.name = "reserved", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_256K + SZ_64K, |
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}, |
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[5] = { |
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.name = "kernel", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_2M + SZ_1M, |
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}, |
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[6] = { |
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.name = "fpga", |
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.offset = MTDPART_OFS_APPEND, |
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.size = SZ_2M, |
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}, |
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[7] = { |
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.name = "spare", |
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.offset = MTDPART_OFS_APPEND, |
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.size = MTDPART_SIZ_FULL, |
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}, |
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}; |
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static struct flash_platform_data mityomapl138_spi_flash_data = { |
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.name = "m25p80", |
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.parts = spi_flash_partitions, |
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.nr_parts = ARRAY_SIZE(spi_flash_partitions), |
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.type = "m24p64", |
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}; |
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static struct davinci_spi_config spi_eprom_config = { |
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.io_type = SPI_IO_TYPE_DMA, |
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.c2tdelay = 8, |
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.t2cdelay = 8, |
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}; |
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static struct spi_board_info mityomapl138_spi_flash_info[] = { |
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{ |
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.modalias = "m25p80", |
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.platform_data = &mityomapl138_spi_flash_data, |
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.controller_data = &spi_eprom_config, |
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.mode = SPI_MODE_0, |
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.max_speed_hz = 30000000, |
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.bus_num = 1, |
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.chip_select = 0, |
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}, |
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}; |
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/* |
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* MityDSP-L138 includes a 256 MByte large-page NAND flash |
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* (128K blocks). |
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*/ |
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static struct mtd_partition mityomapl138_nandflash_partition[] = { |
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{ |
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.name = "rootfs", |
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.offset = 0, |
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.size = SZ_128M, |
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.mask_flags = 0, /* MTD_WRITEABLE, */ |
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}, |
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{ |
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.name = "homefs", |
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.offset = MTDPART_OFS_APPEND, |
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.size = MTDPART_SIZ_FULL, |
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.mask_flags = 0, |
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}, |
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}; |
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static struct davinci_nand_pdata mityomapl138_nandflash_data = { |
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.core_chipsel = 1, |
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.parts = mityomapl138_nandflash_partition, |
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.nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), |
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.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, |
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.bbt_options = NAND_BBT_USE_FLASH, |
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.options = NAND_BUSWIDTH_16, |
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.ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ |
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}; |
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static struct resource mityomapl138_nandflash_resource[] = { |
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{ |
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.start = DA8XX_AEMIF_CS3_BASE, |
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.end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, |
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.flags = IORESOURCE_MEM, |
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}, |
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{ |
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.start = DA8XX_AEMIF_CTL_BASE, |
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.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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static struct platform_device mityomapl138_aemif_devices[] = { |
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{ |
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.name = "davinci_nand", |
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.id = 1, |
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.dev = { |
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.platform_data = &mityomapl138_nandflash_data, |
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}, |
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.num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), |
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.resource = mityomapl138_nandflash_resource, |
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}, |
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}; |
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static struct resource mityomapl138_aemif_resources[] = { |
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{ |
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.start = DA8XX_AEMIF_CTL_BASE, |
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.end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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static struct aemif_abus_data mityomapl138_aemif_abus_data[] = { |
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{ |
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.cs = 1, |
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}, |
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}; |
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static struct aemif_platform_data mityomapl138_aemif_pdata = { |
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.abus_data = mityomapl138_aemif_abus_data, |
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.num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data), |
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.sub_devices = mityomapl138_aemif_devices, |
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.num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices), |
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}; |
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static struct platform_device mityomapl138_aemif_device = { |
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.name = "ti-aemif", |
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.id = -1, |
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.dev = { |
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.platform_data = &mityomapl138_aemif_pdata, |
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}, |
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.resource = mityomapl138_aemif_resources, |
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.num_resources = ARRAY_SIZE(mityomapl138_aemif_resources), |
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}; |
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static void __init mityomapl138_setup_nand(void) |
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{ |
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if (platform_device_register(&mityomapl138_aemif_device)) |
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pr_warn("%s: Cannot register AEMIF device\n", __func__); |
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} |
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|
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static const short mityomap_mii_pins[] = { |
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DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, |
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DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, |
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DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, |
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DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, |
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DA850_MDIO_D, |
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-1 |
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}; |
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|
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static const short mityomap_rmii_pins[] = { |
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DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, |
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DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, |
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DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, |
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DA850_MDIO_D, |
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-1 |
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}; |
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|
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static void __init mityomapl138_config_emac(void) |
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{ |
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void __iomem *cfg_chip3_base; |
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int ret; |
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u32 val; |
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struct davinci_soc_info *soc_info = &davinci_soc_info; |
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|
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soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ |
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|
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cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); |
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val = __raw_readl(cfg_chip3_base); |
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|
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if (soc_info->emac_pdata->rmii_en) { |
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val |= BIT(8); |
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ret = davinci_cfg_reg_list(mityomap_rmii_pins); |
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pr_info("RMII PHY configured\n"); |
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} else { |
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val &= ~BIT(8); |
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ret = davinci_cfg_reg_list(mityomap_mii_pins); |
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pr_info("MII PHY configured\n"); |
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} |
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|
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if (ret) { |
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pr_warn("mii/rmii mux setup failed: %d\n", ret); |
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return; |
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} |
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|
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/* configure the CFGCHIP3 register for RMII or MII */ |
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__raw_writel(val, cfg_chip3_base); |
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|
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soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; |
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|
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ret = da8xx_register_emac(); |
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if (ret) |
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pr_warn("emac registration failed: %d\n", ret); |
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} |
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|
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static void __init mityomapl138_init(void) |
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{ |
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int ret; |
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|
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da850_register_clocks(); |
|
|
|
/* for now, no special EDMA channels are reserved */ |
|
ret = da850_register_edma(NULL); |
|
if (ret) |
|
pr_warn("edma registration failed: %d\n", ret); |
|
|
|
ret = da8xx_register_watchdog(); |
|
if (ret) |
|
pr_warn("watchdog registration failed: %d\n", ret); |
|
|
|
davinci_serial_init(da8xx_serial_device); |
|
|
|
nvmem_register_notifier(&mityomapl138_nvmem_notifier); |
|
nvmem_add_cell_table(&mityomapl138_nvmem_cell_table); |
|
nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1); |
|
|
|
ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); |
|
if (ret) |
|
pr_warn("i2c0 registration failed: %d\n", ret); |
|
|
|
ret = pmic_tps65023_init(); |
|
if (ret) |
|
pr_warn("TPS65023 PMIC init failed: %d\n", ret); |
|
|
|
mityomapl138_setup_nand(); |
|
|
|
ret = spi_register_board_info(mityomapl138_spi_flash_info, |
|
ARRAY_SIZE(mityomapl138_spi_flash_info)); |
|
if (ret) |
|
pr_warn("spi info registration failed: %d\n", ret); |
|
|
|
ret = da8xx_register_spi_bus(1, |
|
ARRAY_SIZE(mityomapl138_spi_flash_info)); |
|
if (ret) |
|
pr_warn("spi 1 registration failed: %d\n", ret); |
|
|
|
mityomapl138_config_emac(); |
|
|
|
ret = da8xx_register_rtc(); |
|
if (ret) |
|
pr_warn("rtc setup failed: %d\n", ret); |
|
|
|
ret = da8xx_register_cpuidle(); |
|
if (ret) |
|
pr_warn("cpuidle registration failed: %d\n", ret); |
|
|
|
davinci_pm_init(); |
|
} |
|
|
|
#ifdef CONFIG_SERIAL_8250_CONSOLE |
|
static int __init mityomapl138_console_init(void) |
|
{ |
|
if (!machine_is_mityomapl138()) |
|
return 0; |
|
|
|
return add_preferred_console("ttyS", 1, "115200"); |
|
} |
|
console_initcall(mityomapl138_console_init); |
|
#endif |
|
|
|
static void __init mityomapl138_map_io(void) |
|
{ |
|
da850_init(); |
|
} |
|
|
|
MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") |
|
.atag_offset = 0x100, |
|
.map_io = mityomapl138_map_io, |
|
.init_irq = da850_init_irq, |
|
.init_time = da850_init_time, |
|
.init_machine = mityomapl138_init, |
|
.init_late = davinci_init_late, |
|
.dma_zone_size = SZ_128M, |
|
MACHINE_END
|
|
|