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711 lines
15 KiB
711 lines
15 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* arch/arm/mach-at91/pm_slow_clock.S |
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* |
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* Copyright (C) 2006 Savin Zlobec |
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* |
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* AT91SAM9 support: |
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* Copyright (C) 2007 Anti Sullin <anti.sullin@artecdesign.ee> |
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*/ |
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#include <linux/linkage.h> |
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#include <linux/clk/at91_pmc.h> |
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#include "pm.h" |
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#include "pm_data-offsets.h" |
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#define SRAMC_SELF_FRESH_ACTIVE 0x01 |
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#define SRAMC_SELF_FRESH_EXIT 0x00 |
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pmc .req r0 |
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tmp1 .req r4 |
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tmp2 .req r5 |
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tmp3 .req r6 |
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/* |
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* Wait until master clock is ready (after switching master clock source) |
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*/ |
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.macro wait_mckrdy |
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1: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MCKRDY |
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beq 1b |
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.endm |
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/* |
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* Wait until master oscillator has stabilized. |
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*/ |
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.macro wait_moscrdy |
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1: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCS |
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beq 1b |
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.endm |
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/* |
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* Wait for main oscillator selection is done |
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*/ |
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.macro wait_moscsels |
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1: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCSELS |
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beq 1b |
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.endm |
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/* |
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* Put the processor to enter the idle state |
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*/ |
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.macro at91_cpu_idle |
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#if defined(CONFIG_CPU_V7) |
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mov tmp1, #AT91_PMC_PCK |
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str tmp1, [pmc, #AT91_PMC_SCDR] |
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dsb |
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wfi @ Wait For Interrupt |
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#else |
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mcr p15, 0, tmp1, c7, c0, 4 |
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#endif |
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.endm |
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.text |
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.arm |
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/* |
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* void at91_suspend_sram_fn(struct at91_pm_data*) |
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* @input param: |
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* @r0: base address of struct at91_pm_data |
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*/ |
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/* at91_pm_suspend_in_sram must be 8-byte aligned per the requirements of fncpy() */ |
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.align 3 |
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ENTRY(at91_pm_suspend_in_sram) |
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/* Save registers on stack */ |
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stmfd sp!, {r4 - r12, lr} |
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/* Drain write buffer */ |
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mov tmp1, #0 |
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mcr p15, 0, tmp1, c7, c10, 4 |
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ldr tmp1, [r0, #PM_DATA_PMC] |
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str tmp1, .pmc_base |
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ldr tmp1, [r0, #PM_DATA_RAMC0] |
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str tmp1, .sramc_base |
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ldr tmp1, [r0, #PM_DATA_RAMC1] |
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str tmp1, .sramc1_base |
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ldr tmp1, [r0, #PM_DATA_MEMCTRL] |
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str tmp1, .memtype |
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ldr tmp1, [r0, #PM_DATA_MODE] |
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str tmp1, .pm_mode |
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ldr tmp1, [r0, #PM_DATA_PMC_MCKR_OFFSET] |
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str tmp1, .mckr_offset |
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ldr tmp1, [r0, #PM_DATA_PMC_VERSION] |
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str tmp1, .pmc_version |
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/* Both ldrne below are here to preload their address in the TLB */ |
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ldr tmp1, [r0, #PM_DATA_SHDWC] |
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str tmp1, .shdwc |
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cmp tmp1, #0 |
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ldrne tmp2, [tmp1, #0] |
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ldr tmp1, [r0, #PM_DATA_SFRBU] |
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str tmp1, .sfrbu |
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cmp tmp1, #0 |
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ldrne tmp2, [tmp1, #0x10] |
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/* Active the self-refresh mode */ |
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mov r0, #SRAMC_SELF_FRESH_ACTIVE |
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bl at91_sramc_self_refresh |
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ldr r0, .pm_mode |
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cmp r0, #AT91_PM_STANDBY |
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beq standby |
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cmp r0, #AT91_PM_BACKUP |
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beq backup_mode |
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bl at91_ulp_mode |
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b exit_suspend |
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standby: |
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/* Wait for interrupt */ |
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ldr pmc, .pmc_base |
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at91_cpu_idle |
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b exit_suspend |
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backup_mode: |
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bl at91_backup_mode |
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b exit_suspend |
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exit_suspend: |
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/* Exit the self-refresh mode */ |
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mov r0, #SRAMC_SELF_FRESH_EXIT |
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bl at91_sramc_self_refresh |
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/* Restore registers, and return */ |
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ldmfd sp!, {r4 - r12, pc} |
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ENDPROC(at91_pm_suspend_in_sram) |
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ENTRY(at91_backup_mode) |
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/* Switch the master clock source to slow clock. */ |
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ldr pmc, .pmc_base |
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ldr tmp2, .mckr_offset |
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ldr tmp1, [pmc, tmp2] |
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bic tmp1, tmp1, #AT91_PMC_CSS |
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str tmp1, [pmc, tmp2] |
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wait_mckrdy |
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/*BUMEN*/ |
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ldr r0, .sfrbu |
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mov tmp1, #0x1 |
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str tmp1, [r0, #0x10] |
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/* Shutdown */ |
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ldr r0, .shdwc |
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mov tmp1, #0xA5000000 |
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add tmp1, tmp1, #0x1 |
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str tmp1, [r0, #0] |
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ENDPROC(at91_backup_mode) |
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.macro at91_pm_ulp0_mode |
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ldr pmc, .pmc_base |
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ldr tmp2, .pm_mode |
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ldr tmp3, .mckr_offset |
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/* Check if ULP0 fast variant has been requested. */ |
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cmp tmp2, #AT91_PM_ULP0_FAST |
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bne 0f |
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/* Set highest prescaler for power saving */ |
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ldr tmp1, [pmc, tmp3] |
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bic tmp1, tmp1, #AT91_PMC_PRES |
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orr tmp1, tmp1, #AT91_PMC_PRES_64 |
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str tmp1, [pmc, tmp3] |
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wait_mckrdy |
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b 1f |
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0: |
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/* Turn off the crystal oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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bic tmp1, tmp1, #AT91_PMC_MOSCEN |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Save RC oscillator state */ |
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ldr tmp1, [pmc, #AT91_PMC_SR] |
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str tmp1, .saved_osc_status |
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tst tmp1, #AT91_PMC_MOSCRCS |
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bne 1f |
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/* Turn off RC oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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bic tmp1, tmp1, #AT91_PMC_MOSCRCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Wait main RC disabled done */ |
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2: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCRCS |
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bne 2b |
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/* Wait for interrupt */ |
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1: at91_cpu_idle |
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/* Check if ULP0 fast variant has been requested. */ |
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cmp tmp2, #AT91_PM_ULP0_FAST |
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bne 5f |
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/* Set lowest prescaler for fast resume. */ |
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ldr tmp1, [pmc, tmp3] |
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bic tmp1, tmp1, #AT91_PMC_PRES |
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str tmp1, [pmc, tmp3] |
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wait_mckrdy |
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b 6f |
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5: /* Restore RC oscillator state */ |
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ldr tmp1, .saved_osc_status |
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tst tmp1, #AT91_PMC_MOSCRCS |
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beq 4f |
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/* Turn on RC oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_MOSCRCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Wait main RC stabilization */ |
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3: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCRCS |
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beq 3b |
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/* Turn on the crystal oscillator */ |
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4: ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_MOSCEN |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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wait_moscrdy |
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6: |
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.endm |
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/** |
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* Note: This procedure only applies on the platform which uses |
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* the external crystal oscillator as a main clock source. |
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*/ |
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.macro at91_pm_ulp1_mode |
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ldr pmc, .pmc_base |
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ldr tmp2, .mckr_offset |
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/* Save RC oscillator state and check if it is enabled. */ |
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ldr tmp1, [pmc, #AT91_PMC_SR] |
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str tmp1, .saved_osc_status |
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tst tmp1, #AT91_PMC_MOSCRCS |
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bne 2f |
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/* Enable RC oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_MOSCRCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Wait main RC stabilization */ |
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1: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCRCS |
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beq 1b |
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/* Switch the main clock source to 12-MHz RC oscillator */ |
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2: ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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bic tmp1, tmp1, #AT91_PMC_MOSCSEL |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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wait_moscsels |
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/* Disable the crystal oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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bic tmp1, tmp1, #AT91_PMC_MOSCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Switch the master clock source to main clock */ |
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ldr tmp1, [pmc, tmp2] |
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bic tmp1, tmp1, #AT91_PMC_CSS |
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN |
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str tmp1, [pmc, tmp2] |
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wait_mckrdy |
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/* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_WAITMODE |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Quirk for SAM9X60's PMC */ |
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nop |
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nop |
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wait_mckrdy |
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/* Enable the crystal oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_MOSCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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wait_moscrdy |
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/* Switch the master clock source to slow clock */ |
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ldr tmp1, [pmc, tmp2] |
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bic tmp1, tmp1, #AT91_PMC_CSS |
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str tmp1, [pmc, tmp2] |
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wait_mckrdy |
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/* Switch main clock source to crystal oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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orr tmp1, tmp1, #AT91_PMC_MOSCSEL |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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wait_moscsels |
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/* Switch the master clock source to main clock */ |
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ldr tmp1, [pmc, tmp2] |
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bic tmp1, tmp1, #AT91_PMC_CSS |
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN |
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str tmp1, [pmc, tmp2] |
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wait_mckrdy |
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/* Restore RC oscillator state */ |
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ldr tmp1, .saved_osc_status |
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tst tmp1, #AT91_PMC_MOSCRCS |
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bne 3f |
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/* Disable RC oscillator */ |
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ldr tmp1, [pmc, #AT91_CKGR_MOR] |
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bic tmp1, tmp1, #AT91_PMC_MOSCRCEN |
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bic tmp1, tmp1, #AT91_PMC_KEY_MASK |
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orr tmp1, tmp1, #AT91_PMC_KEY |
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str tmp1, [pmc, #AT91_CKGR_MOR] |
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/* Wait RC oscillator disable done */ |
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4: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_MOSCRCS |
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bne 4b |
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3: |
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.endm |
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.macro at91_plla_disable |
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/* Save PLLA setting and disable it */ |
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ldr tmp1, .pmc_version |
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cmp tmp1, #AT91_PMC_V1 |
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beq 1f |
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#ifdef CONFIG_SOC_SAM9X60 |
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/* Save PLLA settings. */ |
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ldr tmp2, [pmc, #AT91_PMC_PLL_UPDT] |
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bic tmp2, tmp2, #AT91_PMC_PLL_UPDT_ID |
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str tmp2, [pmc, #AT91_PMC_PLL_UPDT] |
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/* save div. */ |
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mov tmp1, #0 |
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ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL0] |
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bic tmp2, tmp2, #0xffffff00 |
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orr tmp1, tmp1, tmp2 |
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/* save mul. */ |
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ldr tmp2, [pmc, #AT91_PMC_PLL_CTRL1] |
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bic tmp2, tmp2, #0xffffff |
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orr tmp1, tmp1, tmp2 |
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str tmp1, .saved_pllar |
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/* step 2. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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/* step 3. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK |
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orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL |
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str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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/* step 4. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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/* step 5. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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bic tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL |
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str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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/* step 7. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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b 2f |
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#endif |
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1: /* Save PLLA setting and disable it */ |
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ldr tmp1, [pmc, #AT91_CKGR_PLLAR] |
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str tmp1, .saved_pllar |
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/* Disable PLLA. */ |
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mov tmp1, #AT91_PMC_PLLCOUNT |
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orr tmp1, tmp1, #(1 << 29) /* bit 29 always set */ |
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str tmp1, [pmc, #AT91_CKGR_PLLAR] |
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2: |
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.endm |
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.macro at91_plla_enable |
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ldr tmp2, .saved_pllar |
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ldr tmp3, .pmc_version |
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cmp tmp3, #AT91_PMC_V1 |
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beq 4f |
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#ifdef CONFIG_SOC_SAM9X60 |
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/* step 1. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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/* step 2. */ |
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ldr tmp1, =AT91_PMC_PLL_ACR_DEFAULT_PLLA |
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str tmp1, [pmc, #AT91_PMC_PLL_ACR] |
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/* step 3. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL1] |
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mov tmp3, tmp2 |
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bic tmp3, tmp3, #0xffffff |
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orr tmp1, tmp1, tmp3 |
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str tmp1, [pmc, #AT91_PMC_PLL_CTRL1] |
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/* step 8. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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/* step 9. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENLOCK |
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orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLL |
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orr tmp1, tmp1, #AT91_PMC_PLL_CTRL0_ENPLLCK |
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bic tmp1, tmp1, #0xff |
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mov tmp3, tmp2 |
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bic tmp3, tmp3, #0xffffff00 |
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orr tmp1, tmp1, tmp3 |
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str tmp1, [pmc, #AT91_PMC_PLL_CTRL0] |
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/* step 10. */ |
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ldr tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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orr tmp1, tmp1, #AT91_PMC_PLL_UPDT_UPDATE |
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bic tmp1, tmp1, #AT91_PMC_PLL_UPDT_ID |
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str tmp1, [pmc, #AT91_PMC_PLL_UPDT] |
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/* step 11. */ |
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3: ldr tmp1, [pmc, #AT91_PMC_PLL_ISR0] |
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tst tmp1, #0x1 |
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beq 3b |
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b 2f |
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#endif |
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/* Restore PLLA setting */ |
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4: str tmp2, [pmc, #AT91_CKGR_PLLAR] |
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/* Enable PLLA. */ |
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tst tmp2, #(AT91_PMC_MUL & 0xff0000) |
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bne 1f |
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tst tmp2, #(AT91_PMC_MUL & ~0xff0000) |
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beq 2f |
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1: ldr tmp1, [pmc, #AT91_PMC_SR] |
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tst tmp1, #AT91_PMC_LOCKA |
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beq 1b |
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2: |
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.endm |
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ENTRY(at91_ulp_mode) |
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ldr pmc, .pmc_base |
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ldr tmp2, .mckr_offset |
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ldr tmp3, .pm_mode |
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/* Save Master clock setting */ |
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ldr tmp1, [pmc, tmp2] |
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str tmp1, .saved_mckr |
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/* |
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* Set master clock source to: |
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* - MAINCK if using ULP0 fast variant |
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* - slow clock, otherwise |
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*/ |
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bic tmp1, tmp1, #AT91_PMC_CSS |
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cmp tmp3, #AT91_PM_ULP0_FAST |
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bne save_mck |
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orr tmp1, tmp1, #AT91_PMC_CSS_MAIN |
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save_mck: |
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str tmp1, [pmc, tmp2] |
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wait_mckrdy |
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at91_plla_disable |
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cmp tmp3, #AT91_PM_ULP1 |
|
beq ulp1_mode |
|
|
|
at91_pm_ulp0_mode |
|
b ulp_exit |
|
|
|
ulp1_mode: |
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at91_pm_ulp1_mode |
|
b ulp_exit |
|
|
|
ulp_exit: |
|
ldr pmc, .pmc_base |
|
|
|
at91_plla_enable |
|
|
|
/* |
|
* Restore master clock setting |
|
*/ |
|
ldr tmp1, .mckr_offset |
|
ldr tmp2, .saved_mckr |
|
str tmp2, [pmc, tmp1] |
|
|
|
wait_mckrdy |
|
|
|
mov pc, lr |
|
ENDPROC(at91_ulp_mode) |
|
|
|
/* |
|
* void at91_sramc_self_refresh(unsigned int is_active) |
|
* |
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* @input param: |
|
* @r0: 1 - active self-refresh mode |
|
* 0 - exit self-refresh mode |
|
* register usage: |
|
* @r1: memory type |
|
* @r2: base address of the sram controller |
|
*/ |
|
|
|
ENTRY(at91_sramc_self_refresh) |
|
ldr r1, .memtype |
|
ldr r2, .sramc_base |
|
|
|
cmp r1, #AT91_MEMCTRL_MC |
|
bne ddrc_sf |
|
|
|
/* |
|
* at91rm9200 Memory controller |
|
*/ |
|
|
|
/* |
|
* For exiting the self-refresh mode, do nothing, |
|
* automatically exit the self-refresh mode. |
|
*/ |
|
tst r0, #SRAMC_SELF_FRESH_ACTIVE |
|
beq exit_sramc_sf |
|
|
|
/* Active SDRAM self-refresh mode */ |
|
mov r3, #1 |
|
str r3, [r2, #AT91_MC_SDRAMC_SRR] |
|
b exit_sramc_sf |
|
|
|
ddrc_sf: |
|
cmp r1, #AT91_MEMCTRL_DDRSDR |
|
bne sdramc_sf |
|
|
|
/* |
|
* DDR Memory controller |
|
*/ |
|
tst r0, #SRAMC_SELF_FRESH_ACTIVE |
|
beq ddrc_exit_sf |
|
|
|
/* LPDDR1 --> force DDR2 mode during self-refresh */ |
|
ldr r3, [r2, #AT91_DDRSDRC_MDR] |
|
str r3, .saved_sam9_mdr |
|
bic r3, r3, #~AT91_DDRSDRC_MD |
|
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR |
|
ldreq r3, [r2, #AT91_DDRSDRC_MDR] |
|
biceq r3, r3, #AT91_DDRSDRC_MD |
|
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 |
|
streq r3, [r2, #AT91_DDRSDRC_MDR] |
|
|
|
/* Active DDRC self-refresh mode */ |
|
ldr r3, [r2, #AT91_DDRSDRC_LPR] |
|
str r3, .saved_sam9_lpr |
|
bic r3, r3, #AT91_DDRSDRC_LPCB |
|
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH |
|
str r3, [r2, #AT91_DDRSDRC_LPR] |
|
|
|
/* If using the 2nd ddr controller */ |
|
ldr r2, .sramc1_base |
|
cmp r2, #0 |
|
beq no_2nd_ddrc |
|
|
|
ldr r3, [r2, #AT91_DDRSDRC_MDR] |
|
str r3, .saved_sam9_mdr1 |
|
bic r3, r3, #~AT91_DDRSDRC_MD |
|
cmp r3, #AT91_DDRSDRC_MD_LOW_POWER_DDR |
|
ldreq r3, [r2, #AT91_DDRSDRC_MDR] |
|
biceq r3, r3, #AT91_DDRSDRC_MD |
|
orreq r3, r3, #AT91_DDRSDRC_MD_DDR2 |
|
streq r3, [r2, #AT91_DDRSDRC_MDR] |
|
|
|
/* Active DDRC self-refresh mode */ |
|
ldr r3, [r2, #AT91_DDRSDRC_LPR] |
|
str r3, .saved_sam9_lpr1 |
|
bic r3, r3, #AT91_DDRSDRC_LPCB |
|
orr r3, r3, #AT91_DDRSDRC_LPCB_SELF_REFRESH |
|
str r3, [r2, #AT91_DDRSDRC_LPR] |
|
|
|
no_2nd_ddrc: |
|
b exit_sramc_sf |
|
|
|
ddrc_exit_sf: |
|
/* Restore MDR in case of LPDDR1 */ |
|
ldr r3, .saved_sam9_mdr |
|
str r3, [r2, #AT91_DDRSDRC_MDR] |
|
/* Restore LPR on AT91 with DDRAM */ |
|
ldr r3, .saved_sam9_lpr |
|
str r3, [r2, #AT91_DDRSDRC_LPR] |
|
|
|
/* If using the 2nd ddr controller */ |
|
ldr r2, .sramc1_base |
|
cmp r2, #0 |
|
ldrne r3, .saved_sam9_mdr1 |
|
strne r3, [r2, #AT91_DDRSDRC_MDR] |
|
ldrne r3, .saved_sam9_lpr1 |
|
strne r3, [r2, #AT91_DDRSDRC_LPR] |
|
|
|
b exit_sramc_sf |
|
|
|
/* |
|
* SDRAMC Memory controller |
|
*/ |
|
sdramc_sf: |
|
tst r0, #SRAMC_SELF_FRESH_ACTIVE |
|
beq sdramc_exit_sf |
|
|
|
/* Active SDRAMC self-refresh mode */ |
|
ldr r3, [r2, #AT91_SDRAMC_LPR] |
|
str r3, .saved_sam9_lpr |
|
bic r3, r3, #AT91_SDRAMC_LPCB |
|
orr r3, r3, #AT91_SDRAMC_LPCB_SELF_REFRESH |
|
str r3, [r2, #AT91_SDRAMC_LPR] |
|
|
|
sdramc_exit_sf: |
|
ldr r3, .saved_sam9_lpr |
|
str r3, [r2, #AT91_SDRAMC_LPR] |
|
|
|
exit_sramc_sf: |
|
mov pc, lr |
|
ENDPROC(at91_sramc_self_refresh) |
|
|
|
.pmc_base: |
|
.word 0 |
|
.sramc_base: |
|
.word 0 |
|
.sramc1_base: |
|
.word 0 |
|
.shdwc: |
|
.word 0 |
|
.sfrbu: |
|
.word 0 |
|
.memtype: |
|
.word 0 |
|
.pm_mode: |
|
.word 0 |
|
.mckr_offset: |
|
.word 0 |
|
.pmc_version: |
|
.word 0 |
|
.saved_mckr: |
|
.word 0 |
|
.saved_pllar: |
|
.word 0 |
|
.saved_sam9_lpr: |
|
.word 0 |
|
.saved_sam9_lpr1: |
|
.word 0 |
|
.saved_sam9_mdr: |
|
.word 0 |
|
.saved_sam9_mdr1: |
|
.word 0 |
|
.saved_osc_status: |
|
.word 0 |
|
|
|
ENTRY(at91_pm_suspend_in_sram_sz) |
|
.word .-at91_pm_suspend_in_sram
|
|
|