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133 lines
3.2 KiB
133 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ARM_MPU_H |
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#define __ARM_MPU_H |
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/* MPUIR layout */ |
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#define MPUIR_nU 1 |
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#define MPUIR_DREGION 8 |
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#define MPUIR_IREGION 16 |
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#define MPUIR_DREGION_SZMASK (0xFF << MPUIR_DREGION) |
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#define MPUIR_IREGION_SZMASK (0xFF << MPUIR_IREGION) |
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/* ID_MMFR0 data relevant to MPU */ |
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#define MMFR0_PMSA (0xF << 4) |
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#define MMFR0_PMSAv7 (3 << 4) |
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#define MMFR0_PMSAv8 (4 << 4) |
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/* MPU D/I Size Register fields */ |
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#define PMSAv7_RSR_SZ 1 |
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#define PMSAv7_RSR_EN 0 |
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#define PMSAv7_RSR_SD 8 |
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/* Number of subregions (SD) */ |
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#define PMSAv7_NR_SUBREGS 8 |
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#define PMSAv7_MIN_SUBREG_SIZE 256 |
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/* The D/I RSR value for an enabled region spanning the whole of memory */ |
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#define PMSAv7_RSR_ALL_MEM 63 |
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/* Individual bits in the DR/IR ACR */ |
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#define PMSAv7_ACR_XN (1 << 12) |
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#define PMSAv7_ACR_SHARED (1 << 2) |
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/* C, B and TEX[2:0] bits only have semantic meanings when grouped */ |
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#define PMSAv7_RGN_CACHEABLE 0xB |
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#define PMSAv7_RGN_SHARED_CACHEABLE (PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED) |
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#define PMSAv7_RGN_STRONGLY_ORDERED 0 |
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/* Main region should only be shared for SMP */ |
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#ifdef CONFIG_SMP |
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#define PMSAv7_RGN_NORMAL (PMSAv7_RGN_CACHEABLE | PMSAv7_ACR_SHARED) |
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#else |
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#define PMSAv7_RGN_NORMAL PMSAv7_RGN_CACHEABLE |
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#endif |
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/* Access permission bits of ACR (only define those that we use)*/ |
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#define PMSAv7_AP_PL1RO_PL0NA (0x5 << 8) |
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#define PMSAv7_AP_PL1RW_PL0RW (0x3 << 8) |
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#define PMSAv7_AP_PL1RW_PL0R0 (0x2 << 8) |
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#define PMSAv7_AP_PL1RW_PL0NA (0x1 << 8) |
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#define PMSAv8_BAR_XN 1 |
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#define PMSAv8_LAR_EN 1 |
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#define PMSAv8_LAR_IDX(n) (((n) & 0x7) << 1) |
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#define PMSAv8_AP_PL1RW_PL0NA (0 << 1) |
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#define PMSAv8_AP_PL1RW_PL0RW (1 << 1) |
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#define PMSAv8_AP_PL1RO_PL0RO (3 << 1) |
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#ifdef CONFIG_SMP |
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#define PMSAv8_RGN_SHARED (3 << 3) // inner sharable |
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#else |
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#define PMSAv8_RGN_SHARED (0 << 3) |
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#endif |
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#define PMSAv8_RGN_DEVICE_nGnRnE 0 |
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#define PMSAv8_RGN_NORMAL 1 |
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#define PMSAv8_MAIR(attr, mt) ((attr) << ((mt) * 8)) |
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#ifdef CONFIG_CPU_V7M |
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#define PMSAv8_MINALIGN 32 |
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#else |
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#define PMSAv8_MINALIGN 64 |
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#endif |
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/* For minimal static MPU region configurations */ |
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#define PMSAv7_PROBE_REGION 0 |
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#define PMSAv7_BG_REGION 1 |
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#define PMSAv7_RAM_REGION 2 |
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#define PMSAv7_ROM_REGION 3 |
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/* Fixed for PMSAv8 only */ |
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#define PMSAv8_XIP_REGION 0 |
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#define PMSAv8_KERNEL_REGION 1 |
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/* Maximum number of regions Linux is interested in */ |
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#define MPU_MAX_REGIONS 16 |
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#define PMSAv7_DATA_SIDE 0 |
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#define PMSAv7_INSTR_SIDE 1 |
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#ifndef __ASSEMBLY__ |
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struct mpu_rgn { |
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/* Assume same attributes for d/i-side */ |
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union { |
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u32 drbar; /* PMSAv7 */ |
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u32 prbar; /* PMSAv8 */ |
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}; |
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union { |
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u32 drsr; /* PMSAv7 */ |
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u32 prlar; /* PMSAv8 */ |
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}; |
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union { |
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u32 dracr; /* PMSAv7 */ |
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u32 unused; /* not used in PMSAv8 */ |
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}; |
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}; |
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struct mpu_rgn_info { |
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unsigned int used; |
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struct mpu_rgn rgns[MPU_MAX_REGIONS]; |
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}; |
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extern struct mpu_rgn_info mpu_rgn_info; |
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#ifdef CONFIG_ARM_MPU |
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extern void __init pmsav7_adjust_lowmem_bounds(void); |
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extern void __init pmsav8_adjust_lowmem_bounds(void); |
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extern void __init pmsav7_setup(void); |
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extern void __init pmsav8_setup(void); |
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#else |
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static inline void pmsav7_adjust_lowmem_bounds(void) {}; |
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static inline void pmsav8_adjust_lowmem_bounds(void) {}; |
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static inline void pmsav7_setup(void) {}; |
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static inline void pmsav8_setup(void) {}; |
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#endif |
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#endif /* __ASSEMBLY__ */ |
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#endif
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